Error Detection Unit for Return Address Stack Alignment
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Solution Overview
Problem
Data processing apparatuses face performance issues due to broken call-return flows in program instructions, particularly when executing legacy software with changes in assembler syntax, which are not recognized by newer systems, leading to mispredictions in return address predictions.
Innovation Solution
A hardware-based mechanism with an error detection unit identifies missing call or return instructions by comparing return address predictions with resolved addresses and stack content, and performs error correction procedures such as returning popped return addresses to the stack or flushing the stack to maintain correct alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a return address stack is used to generate return address predictions for speculative execution, then instruction fetching and pipelining performance is improved, but the system becomes vulnerable to broken call-return flows in legacy software
Solution Approach 1:
The system implements feedback mechanisms by comparing predicted return addresses with actual resolved return addresses and using this information to detect and correct broken call-return flows. The error detection unit provides feedback about mismatches between predicted and actual return addresses, enabling the system to adapt to legacy software behaviors.
Solution Approach 2:
The system performs preliminary actions by pre-computing return address predictions before actual return instructions are executed. The branch prediction unit generates return address predictions in advance based on the return address stack, allowing the fetch unit to prepare instructions ahead of time while the error detection unit monitors for discrepancies.
2Adaptability or versatility
If software is ported to newer data processing apparatus with updated assembler syntax, then compatibility with legacy software is improved, but return address stack functionality breaks down due to syntax changes
Solution Approach 1:
The error detection unit acts as an intermediary between the return address stack mechanism and the executed program. It monitors the interaction between predicted return addresses and actual resolved addresses, detecting when assembler syntax changes cause broken call-return flows, and providing correction mechanisms to maintain stack alignment.
Solution Approach 2:
The system detects and responds to parameter changes in assembler syntax by monitoring for deviations in call-return instruction patterns. When syntax changes cause broken call-return flows, the error detection unit identifies these as anomalies and triggers correction procedures to restore proper return address stack alignment.
3Reliability
If error correction procedures are implemented to fix broken call-return flows, then return address stack alignment is improved, but device complexity increases
Solution Approach 1:
The error detection and correction functions are merged into the existing branch prediction unit and fetch unit architecture. The error detection unit integrates with the return address stack mechanism, combining multiple functions (prediction, detection, and correction) into a unified hardware structure rather than adding separate independent systems.
Data Source
AI summary
A data processing apparatus and method of data processing are disclosed. A fetch unit retrieves program instructions comprising call instructions and return instructions from memory to be executed by an execution unit. A branch prediction unit generates a return address prediction for an identified return instruction with reference to a return address stack. The branch prediction unit performs a return address push onto said return address stack when the execution unit executes a call instruction and performs a return address pop from the return address stack when the execution unit executes a return instruction. An error detection unit identifies a missing call instruction or a missing return instruction in said program instructions by reference to the return address prediction, a resolved return address indicated by the execution unit when the return instruction is executed and the content of the return address stack.