Error Insertion Circuit for ECC Memory Testing
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Solution Overview
Problem
Existing error correction code (ECC) systems face challenges in determining whether a noisy channel, such as memory, has an error range that can be corrected, which affects resource allocation and error correction capabilities.
Innovation Solution
A device and method that includes an ECC engine and an error insertion circuit to test the error correction capabilities by selectively inserting errors into data, allowing for verification of the error margin in memory systems, enabling efficient resource allocation and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the correctable error amount is increased, then the error correction capability is improved, but the resources and redundancy required increase
Solution Approach 1:
The patent changes the parameter of error insertion position to optimize the testing process. By dynamically selecting different positions for error insertion within the codeword, the system can verify error correction capability across various locations without increasing the overall redundancy amount, thus resolving the contradiction between reliability and resource consumption
2Reliability
If the amount of redundancy added to ECC is increased, then the correctable error amount is improved, but the resource consumption increases
Solution Approach 1:
The patent applies partial action by inserting errors at specific selected positions rather than uniformly across all positions. This allows the system to verify error correction capability with a focused testing approach, avoiding the need to increase redundancy beyond what is minimally required for the specified error correction level
3Reliability
If error insertion testing is performed to verify memory error range, then the reliability verification is improved, but the testing complexity and time increase
Solution Approach 1:
The patent performs preliminary error insertion before the actual memory operation. By pre-inserting errors at selected positions and verifying correction capability in advance, the system can quickly determine whether the memory meets the required error correction specifications without performing extensive testing during actual operation, thus reducing overall testing time
Data Source
AI summary
A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.