Error Mitigation for Resilient Algorithms via Operand Substitution
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Solution Overview
Problem
Existing error handling techniques in storage circuits, such as those used in RAM and registers, are inadequate in addressing transient and intermittent faults, particularly when supply voltages are reduced to lower power consumption, as they increase power consumption and do not correct errors effectively.
Innovation Solution
A method that selectively enables error coping by replacing erroneous operand values with substitute values, such as programmable or last used values, allowing computations to continue without delay, even when errors are detected, thereby enhancing error tolerance in resilient algorithms like neural networks without requiring additional dedicated circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity or ECC checking is used to detect errors in storage circuits, then error detection capability is improved, but additional circuitry and power consumption increase
Solution Approach 1:
The patent extracts the error detection function from dedicated hardware circuitry (parity/ECC circuits) and implements it through software-based error detection instructions executed by the processor. This removes the need for additional error detection hardware, reducing circuit complexity and power consumption while maintaining error detection capability.
Solution Approach 2:
The processor serves dual purposes: it performs both computation and error detection functions. The error detection capability is embedded within the processor's existing instruction execution mechanism, allowing the processor to self-monitor for errors without requiring separate dedicated error detection hardware.
2Reliability
If retry or stop operations are initiated when errors are detected, then error handling is improved, but computation continuity and real-time performance deteriorate
Solution Approach 1:
The patent changes the error handling approach from binary (retry or stop) to a spectrum of responses based on error type and algorithm characteristics. By identifying resilient algorithms that can tolerate certain errors, the system continues execution with modified parameters rather than interrupting, thus maintaining computation continuity while still handling errors appropriately.
Solution Approach 2:
The error handling mechanism is made dynamic by allowing the system to adapt its response based on the specific error conditions and algorithm properties. Rather than a static retry/stop decision, the system dynamically continues execution for resilient algorithms while applying appropriate error mitigation strategies, enabling flexible real-time error handling.
3Use of energy by moving object
If supply voltage is reduced to lower power consumption, then energy efficiency is improved, but circuit reliability and error tolerance worsen
Solution Approach 1:
The patent implements feedback through error detection instructions that monitor computation results for errors. This feedback mechanism allows the system to detect errors caused by reduced supply voltage and apply appropriate error mitigation strategies, enabling reliable operation at lower voltages where traditional circuits would fail.
Solution Approach 2:
The patent replaces hardware-based error prevention mechanisms (which would require higher voltage margins) with software-based error detection and mitigation. This substitution allows the system to operate reliably at lower supply voltages by using instruction-level error detection and resilient algorithm properties rather than hardware redundancy.
4Reliability
If additional circuitry is added to correct errors (such as razor circuits), then error correction capability is improved, but device complexity and die area increase
Solution Approach 1:
The patent makes the processor universal by enabling it to perform both computation and error detection/correction functions through software instructions. This eliminates the need for dedicated error correction hardware circuits, reducing device complexity and die area while maintaining error correction capability through software-based mechanisms.
Solution Approach 2:
The patent extracts the error correction function from dedicated hardware circuits (like razor circuits) and implements it through software instructions executed by the processor. This removes the need for additional error correction hardware, simplifying the circuit design and reducing die area while preserving error correction functionality.
Data Source
AI summary
A method, computer readable medium, and system are disclosed for error coping. The method includes the steps of receiving, by a processing unit, a set of program instructions including a first program instruction that is responsive to error detection, detecting an error in a value of a first operand of the first program instruction, and determining that error coping execution is selectively enabled for the first instruction. The value for the first operand is replaced with a substitute value and the first program instruction is executed by the processing unit.