Error Locator Polynomial Decoding With Adaptive Iteration Skipping
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Solution Overview
Problem
Current data storage devices face inefficiencies in decoding data due to high power consumption and latency caused by iterative decoding processes, particularly in correcting errors in non-volatile memory systems where electrical noise can introduce errors that require extensive clock cycles and power usage.
Innovation Solution
A decoder system that adjusts the length of the error locator polynomial based on error parity, allowing for the condensation of decoding operations by skipping certain iterations and reducing the number of clock cycles required, thereby decreasing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an iterative decoding process is used to locate and correct data errors, then error correction capability is improved, but power consumption increases and decoding latency increases
Solution Approach 1:
The patent applies partial action by performing only the necessary number of iterations in the decoding process. Instead of always executing the full iterative decoding sequence, the system dynamically determines when sufficient error correction has been achieved and terminates early, thus consuming less power while maintaining reliable error correction capability.
Solution Approach 2:
The patent implements feedback mechanisms where the decoding progress is continuously monitored and used to control subsequent decoding iterations. The system uses feedback from syndrome calculations and error location detection to decide whether to continue or terminate the iterative process, optimizing power consumption based on actual decoding needs rather than predetermined iteration counts.
2Reliability
If an iterative decoding process is used to locate and correct data errors, then error correction capability is improved, but decoding latency increases
Solution Approach 1:
The patent applies partial action by performing only the necessary number of iterations in the decoding process. Instead of always executing the full iterative decoding sequence, the system dynamically determines when sufficient error correction has been achieved and terminates early, thus reducing decoding latency while maintaining reliable error correction capability.
Solution Approach 2:
The patent implements feedback mechanisms where the decoding progress is continuously monitored and used to control subsequent decoding iterations. The system uses feedback from syndrome calculations and error location detection to decide whether to continue or terminate the iterative process, optimizing decoding latency based on actual decoding needs rather than predetermined iteration counts.
3Reliability
If the error locator polynomial length is fixed at maximum value, then error correction capability is maintained, but decoding operations cannot be condensed
Solution Approach 1:
The patent applies dynamics by making the error locator polynomial length adaptive rather than fixed. The system dynamically adjusts the polynomial length based on the actual number of errors detected in the data, allowing the decoding process to condense operations when fewer errors are present while maintaining full error correction capability when more errors occur.
Solution Approach 2:
The patent changes the parameter of error locator polynomial length from a fixed maximum value to a dynamic value that adapts to the actual error conditions. By modifying this parameter based on syndrome analysis and error detection results, the system improves decoding operation efficiency without sacrificing error correction capability.
Data Source
AI summary
A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter.