Error Rate Measurement Matrix Scan PCI Express 6

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Solution Overview

Problem

Conventional error rate measurement apparatuses struggle to visually determine the optimum setting for receivers in devices under test compliant with the PCI Express 6 standard during bit error rate measurements, leading to inefficient debugging.

Innovation Solution

An error rate measurement apparatus and method that utilize a matrix scan function to transmit test signals with combinations of coefficient values defined by the PCI Express standard, displaying bit error rates in a color-coded matrix or three-dimensional bird-eye view to identify optimal settings for receivers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a three-dimensional triangular matrix is used to express coefficient values in the PCI Express 6 standard, then the measurement precision of bit error rate is improved, but the ease of operation deteriorates because the optimum setting cannot be visually grasped from the display screen

Engineering Contradiction:
Improvebit error rate measurement precisionVSAvoidease of operation
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent transforms the three-dimensional triangular matrix data into a two-dimensional display format by mapping coefficient combinations to matrix cells. This dimensionality reduction allows the display of bit error rates for multiple coefficient combinations (C-2, C-1, C+1) in a visually accessible 2D grid, resolving the contradiction between maintaining measurement precision and improving ease of operation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the three-dimensional coefficient space into discrete matrix cells, where each cell represents a specific combination of coefficient values. This segmentation allows operators to visually identify optimum settings by comparing bit error rates across individual cells, making the complex 3D data manageable and visually interpretable in 2D.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If conventional matrix scan function is used for PCI Express 6 standard, then the device complexity is reduced, but the productivity deteriorates because debugging cannot be performed efficiently

Engineering Contradiction:
Improvedevice complexityVSAvoidproductivity
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent applies color-coding to different matrix cells based on bit error rate values, enabling rapid visual identification of optimum coefficient combinations. This visual enhancement allows debuggers to quickly locate best settings without manually analyzing numerical data, significantly improving debugging productivity while maintaining conventional device architecture.

Inventive Principle:
Principle #32Color changes

Data Source

PatentUS12253924B2Error rate measurement apparatus and error rate measurement method
Publication Date: 2025.03.18 ANRITSU CORP
  • US12253924B2 patent drawing
  • US12253924B2 patent drawing
  • US12253924B2 patent drawing

AI summary

An error rate measurement apparatus includes an operation display unit and a display control unit. Displays a measurement result when the matrix scan function is executed. The display control unit displays a first coefficient value in a selectable manner by tabs of a number corresponding to the Full Swing value, uses each one of combinations of the first coefficient value, each second coefficient value, and each third coefficient value on the selected table as the cell, displays an error count value and the bit error rate for each cell, which are obtained by the matrix scan function on a display screen in a matrix, and identifies and displays the bit error rate for each cell on the display screen according to an error degree.