Error Repair Location Cache for NAND Flash Memory
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Solution Overview
Problem
As memory systems scale geometrically and use multi-level bit storage, error correction codes (ECC) face challenges in increasing memory area and system latency due to decreased signal margins and non-random memory errors caused by physical coupling issues and defects, particularly in NAND Flash memories.
Innovation Solution
The system detects error-prone locations, stores failure data, and flips the state of the most likely failure-prone bit when ECC saturates, allowing for repeated ECC execution to improve correction probability without increasing memory area or latency, using an error repair location cache to guide the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Error Correction Code (ECC) is used to correct memory errors, then memory reliability is improved, but memory area and READ latency increase
Solution Approach 1:
The system performs preliminary action by detecting and recording error-prone locations during initial memory operations. The error-prone location cache stores information about bits that are likely to fail, allowing the system to proactively flip these bits before they cause actual errors. This preliminary identification and correction approach improves memory reliability without requiring additional ECC overhead during normal operations.
Solution Approach 2:
The error-prone location cache acts as an intermediary between the memory array and the ECC system. Instead of directly increasing ECC capacity, the cache provides intermediate information about which locations are prone to errors. This intermediary structure allows the system to target corrections efficiently, improving reliability without proportionally increasing the memory area dedicated to error correction.
2Reliability
If Error Correction Code (ECC) is used to correct memory errors, then memory reliability is improved, but READ latency increases
Solution Approach 1:
The system performs preliminary action by detecting and recording error-prone locations during initial memory operations. The error-prone location cache stores information about bits that are likely to fail, allowing the system to proactively flip these bits before they cause actual errors. This preliminary identification and correction approach improves memory reliability without requiring additional ECC overhead during normal operations.
Solution Approach 2:
The error-prone location cache enables the memory system to self-service by automatically identifying and correcting its own errors without external intervention. When the cache detects an error-prone location, it automatically flips the corresponding bit, allowing the memory to correct its own errors without requiring additional ECC processing time during reads, thus maintaining low latency while improving reliability.
3Quantity of substance
If multi-level bit storage is used to increase storage capacity, then memory density is improved, but signal margins decrease leading to more errors
Solution Approach 1:
The system performs preliminary action by detecting and recording error-prone locations during initial memory operations. The error-prone location cache stores information about bits that are likely to fail, allowing the system to proactively flip these bits before they cause actual errors. This preliminary identification and correction approach improves memory reliability without requiring additional ECC overhead during normal operations.
Solution Approach 2:
The error-prone location cache implements a feedback mechanism where information about failed or error-prone bits is captured and used to improve future operations. When errors occur in multi-level bit storage, the cache records these locations and uses this feedback to proactively correct similar errors in the future, compensating for the reduced signal margins inherent in high-density storage.
4Reliability
If ECC capacity is increased to correct more errors, then error correction capability is improved, but memory area and system complexity increase
Solution Approach 1:
The error-prone location cache applies local quality by focusing error correction resources on specific locations that are proven to be error-prone, rather than uniformly increasing ECC capacity across the entire memory. The cache identifies and targets only the problematic bits, allowing standard ECC to handle the majority of cases while the cache provides specialized correction for difficult cases, thus improving capability without proportionally increasing overall complexity.
Solution Approach 2:
The system uses partial action by implementing error correction only where needed through the error-prone location cache, rather than applying full-strength ECC to all memory operations. The cache provides additional correction capability selectively for identified error-prone locations, avoiding the overhead of universally increasing ECC capacity while still improving overall error correction capability where it matters most.
Data Source
AI summary
A method for repairing a memory includes executing an Error Correction Code (ECC) for a page of the memory. The page includes a plurality of bits having an inherent number of failed bits equal to or greater than zero. The ECC is configured to correct a correctable number of failed bits from the plurality of bits. A location of a failure prone bit in the page is determined from a cache in response to the correctable number of failed bits being less than the inherent number of failed bits. A state of the failure prone bit is changed to a new state in response to determining the location of the failure prone bit. The ECC is executed in response to the state of the failure prone bit being changed to the new state.