Integrated Error Sampler Circuit for Relaxed DFE Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In serial communication systems, existing error samplers face challenges in meeting decision feedback equalizer (DFE) timing requirements due to the addition of slicers in the data path, which complicates precise delay matching and results in low gain/sensitivity, and the need for separate slicers in the error path requires precise clock path matching that is difficult to achieve.
Innovation Solution
The error sampler integrates slicing and sampling without degeneration resistors, using an fT-doubler-type structure with differential pairs for Vin+ minus Vref+ and Vin- minus Vref-, allowing the same clock signal for both data and error sampling, and includes a common-mode loop to maintain equal common-mode voltages for Vin and Vref, eliminating the need for a separate slicer and relaxing DFE loop timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate slicers are added in the data path and error path to meet DFE timing requirements, then timing precision is improved, but device complexity increases and gain/sensitivity decreases
Solution Approach 1:
The patent combines the slicer and error sampler into a single integrated circuit block. The differential input stage simultaneously performs slicing (comparing Vin against Vref) and error sampling (capturing the difference signal), eliminating the need for separate slicer circuits in both data and error paths. This integration directly reduces device complexity while maintaining timing precision through shared clocking and synchronized operation.
2Manufacturing precision
If separate slicers are added in the data path and error path, then timing precision is improved, but the number of components increases
Solution Approach 1:
The patent merges multiple functional components into a single integrated error sampler circuit. The differential input stage, reference voltage input stage, and sampling latches work together in one circuit block to perform both slicing and error sampling functions, significantly reducing the total number of components compared to having separate slicers in the data path and error path.
Solution Approach 2:
The integrated error sampler circuit performs multiple functions simultaneously: it acts as a slicer by comparing Vin against Vref, it samples the error signal, and it provides timing synchronization for the DFE. This multi-functionality eliminates the need for dedicated separate components, reducing the overall component count while maintaining precise timing control.
3Stability of the object's composition
If degeneration resistors are used in the differential pairs, then stability is improved, but gain/sensitivity decreases
Solution Approach 1:
The patent removes degeneration resistors from the differential pair circuits. By eliminating these resistors, the circuit achieves higher gain and sensitivity in the differential stages. The design compensates for the reduced stability that would normally result from removing degeneration resistors through careful layout matching, temperature compensation techniques, and optimized biasing schemes that maintain circuit stability without requiring additional resistive elements.
Data Source
AI summary
An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.