Error Signaling Windows for Phase-Differential Serial Bus Protocols

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Solution Overview

Problem

Conventional serial bus interfaces, such as I3C protocols, face challenges in error detection and reporting, particularly at high data rates, leading to collisions and reduced data integrity due to the lack of effective mechanisms for identifying errors in phase-differential encoding schemes.

Innovation Solution

The implementation of pre-defined error signaling windows using unique patterns within the data stream allows receiving devices to unequivocally identify errors, enabling timely error detection and reporting, thereby improving communication integrity in high-speed interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional error reporting mechanisms are used on half-duplex serial bus, then error detection capability is provided, but collisions occur and data rates are reduced

Engineering Contradiction:
Improveerror detection capabilityVSAvoiddata rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-defining specific symbol sequences as error signaling windows before transmission occurs. These predetermined sequences reserve specific time slots exclusively for error reporting, allowing receivers to signal errors without interfering with ongoing data transmission. This prevents collisions that would otherwise occur when receivers attempt to interrupt transmission for error reporting, thus maintaining high data rates while ensuring reliable error detection.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If higher clock rates are used to meet throughput demands, then data rate is improved, but timing errors and synchronization issues increase

Engineering Contradiction:
ImprovethroughputVSAvoidtiming accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by pre-defining specific symbol sequences as error signaling windows before transmission occurs. These predetermined sequences reserve specific time slots exclusively for error reporting, allowing receivers to signal errors without interfering with ongoing data transmission. This prevents collisions that would otherwise occur when receivers attempt to interrupt transmission for error reporting, thus maintaining high data rates while ensuring reliable error detection.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If phase-differential encoding is used to increase data rate, then throughput is improved, but error detection complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoiderror detection complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-defining specific symbol sequences as error signaling windows before transmission occurs. These predetermined sequences reserve specific time slots exclusively for error reporting, allowing receivers to signal errors without interfering with ongoing data transmission. This prevents collisions that would otherwise occur when receivers attempt to interrupt transmission for error reporting, thus maintaining high data rates while ensuring reliable error detection.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11531608B2Error signaling windows for phase-differential protocols
Publication Date: 2022.12.20 QUALCOMM INC
  • US11531608B2 patent drawing
  • US11531608B2 patent drawing
  • US11531608B2 patent drawing

AI summary

Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.