Prioritized Error Signature Mapping for Scan Test Cells
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Solution Overview
Problem
Existing methods for fault diagnosis in integrated circuit manufacturing face limitations due to limited observability and inefficiency in mapping failure indications from compactor architectures with few outputs, leading to reduced time efficiency and reliability in identifying failure indicating scan test cells.
Innovation Solution
The method involves generating error signatures by a compactor, assigning them to different signature types based on uniqueness and ease of mapping, and prioritizing their mapping to scan test cells, allowing for efficient identification of failure indicating scan test cells through a prioritized and phased mapping process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If error signatures are mapped without prioritization, then all error signatures can be mapped, but the mapping process requires multiple iterations and reduces time efficiency
Solution Approach 1:
The patent applies preliminary action by classifying error signatures into different types before the mapping process begins. This pre-classification allows the mapping algorithm to prioritize certain error signatures over others, avoiding the need for multiple iterative passes through all error signatures. The classification is performed in advance based on characteristics such as the number of failing bits and their positions, enabling a more efficient single-pass or reduced-pass mapping process.
2Reliability
If all error signatures are mapped with equal priority, then comprehensive coverage is achieved, but the complexity of the mapping process increases and reliability decreases
Solution Approach 1:
The patent applies segmentation by dividing error signatures into distinct types based on their characteristics, such as the number of failing bits and their positions within the signature. This segmentation creates categories (e.g., single-bit errors, multi-bit errors, errors in specific positions) that can be handled by different mapping strategies. By segmenting the problem space, the patent reduces the overall complexity while improving reliability, as each segment can be mapped with appropriate priority and method.
Solution Approach 2:
The patent applies local quality by assigning different mapping priorities and strategies to different types of error signatures based on their specific characteristics. Rather than applying a uniform mapping approach to all error signatures, the patent tailors the mapping process to each error signature type. For example, error signatures with certain patterns may be mapped with higher priority or using specialized algorithms, while others use standard mapping. This localized approach improves overall reliability without requiring complex handling of all cases equally.
3Measurement precision
If error signatures are classified into multiple types, then mapping priority can be determined, but the classification process adds complexity
Solution Approach 1:
The patent applies parameter changes by using specific characteristics of error signatures (such as the number of failing bits, their positions, and patterns) as parameters for classification. These parameters are extracted from the error signature data and used to assign error signatures to different types. The classification system uses these parameters in a systematic way to determine mapping priority, achieving precise fault localization without requiring overly complex classification logic. The parameters naturally present in the error signatures are leveraged rather than introducing additional complex features.
Data Source
AI summary
A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. For each error signature, a priority of the mapping is determined by the signature type the respective error signature has been assigned to.