Error Information Storage Circuit for Semiconductor Error Cell Detection
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Solution Overview
Problem
Current methods for detecting error cells in semiconductor apparatuses are complex and time-consuming, requiring significant duration for testing due to the complexity involved in accessing and identifying error cells.
Innovation Solution
An error information storage circuit that writes test data with opposite levels to adjacent fuse latch sets using a clock and control signal generation circuit, allowing for efficient detection of error cells during the boot-up process or in response to a test mode signal, thereby improving test performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error cell detection methods are used, then error cells can be detected, but the testing time duration increases and test performance decreases
Solution Approach 1:
The patent applies preliminary action by pre-loading test data into fuse latch sets during the boot-up process before normal operation begins. The fuse latch sets are pre-configured with test patterns (such as alternating 0s and 1s) that enable immediate error detection when testing is initiated, eliminating the need to generate and load test data during the actual testing phase. This advance preparation significantly reduces the time required for error cell detection while maintaining detection reliability.
2Measurement precision
If complex testing procedures are implemented to detect error cells, then detection accuracy is maintained, but device complexity and operational complexity increase
Solution Approach 1:
The patent uses copying by creating duplicate copies of test data in the fuse latch sets during boot-up. Instead of complex real-time test generation and comparison circuits, the system copies predetermined test patterns into latch sets that mirror the memory structure. This allows simple read-back and comparison operations during testing, maintaining detection accuracy while dramatically simplifying the testing procedure and reducing the complexity of test control logic.
3Reliability
If fuse latch sets are accessed sequentially for testing, then testing can be performed, but productivity and test throughput are reduced
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple independently testable fuse latch sets. Each fuse latch set can be accessed and tested independently or in parallel, allowing the testing process to be divided into multiple concurrent operations. This segmentation enables higher test throughput by allowing simultaneous testing of different memory regions while maintaining the reliability of each individual test through dedicated latch sets for each segment.
Data Source
AI summary
An error information storage circuit configured to write information stored in a plurality of fuse sets to a plurality of fuse latch sets of a core block and/or to write test data to the plurality of fuse latch sets. The test data is internally generated depending on a fuse clock signal, and the test data has values which cause opposite levels to be written in adjacent latches of the plurality of fuse latch sets.