Error Tolerant Memory Array with PROM-Based Correction
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Solution Overview
Problem
As technology advances, the limitations of shrinking metal geometries and increasing defect generation rates in non-volatile memories (NVMs) pose challenges for error correction in integrated circuit memory, requiring fast and efficient solutions to maintain low failure rates and costs.
Innovation Solution
A method for error correction in memory arrays involves storing error entries in an error PROM, including bit position and correction data, and using a counter to generate unique terms for addressing bit errors, allowing for efficient substitution of corrected data in real-time, even in microsecond time frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If material structural change mechanisms (PCM or ReRAM) are used for non-volatile memory programming, then memory scalability and non-volatility are improved, but defect generation rate increases by orders of magnitude
Solution Approach 1:
The patent pre-programs error correction data into the PROM during manufacturing before the memory device is shipped. This preliminary action creates a lookup table of correct data values that can be rapidly retrieved during operation, eliminating the need for complex real-time error correction algorithms and enabling fast correction of defects generated by PCM/ReRAM mechanisms
Solution Approach 2:
The patent introduces a PROM (programmable read-only memory) as an intermediary component that stores pre-calculated error correction data. This PROM acts as a mediator between the defective NVM array and the correction logic, providing rapid access to correction values without requiring complex processing during memory operations
2Reliability
If enterprise-level error correction solutions are applied to integrated circuit memory, then error correction capability is improved, but manufacturing cost increases due to large volumes of spare memory requirements
Solution Approach 1:
The patent implements error correction on a per-word basis rather than requiring large blocks of spare memory. Each memory word has its own dedicated error correction entry in the PROM, allowing selective correction of only the specific defective words encountered in production, thereby reducing the amount of spare memory needed and lowering manufacturing costs
3Measurement precision
If complex error correction algorithms are implemented in integrated circuit memory, then error correction accuracy is improved, but correction speed decreases beyond microsecond time frames
Solution Approach 1:
The patent pre-computes and stores all error correction data in the PROM during manufacturing. During operation, the system only needs to perform a simple address lookup and data retrieval from the PROM, which occurs in nanoseconds rather than microseconds. This eliminates complex real-time computation while maintaining full error correction capability
Solution Approach 2:
The patent uses a dynamic counter that increments with each memory address accessed, automatically generating the correct address to query in the PROM. This dynamic addressing mechanism enables rapid sequential correction of multiple defective words without requiring complex decision logic, maintaining high-speed operation
Data Source
AI summary
A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.