Error Unbiased Approximate Multiplier for Floating-Point Numbers
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Solution Overview
Problem
Existing approximate multipliers for floating-point numbers in intelligent mobile and wearable devices suffer from high power consumption, large area requirements, and fixed accuracy, lacking a general design method for low error and low power consumption.
Innovation Solution
An error unbiased approximate multiplier for normalized floating-point numbers is designed, comprising a symbol and exponent bit module, a mantissa approximation module with 0-level and multilevel error correction modules, and a normalization module, which performs Exclusive OR operations, mantissa approximation, and error correction to achieve adjustable accuracy and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If approximate multiplication is used to reduce power consumption and area, then power consumption and area are reduced, but calculation accuracy deteriorates
Solution Approach 1:
The multiplication operation is segmented into multiple approximation stages, where each stage processes a portion of the mantissa bits. The method divides the 23-bit mantissa into segments and applies different approximation strategies to each segment, allowing the system to achieve acceptable accuracy with reduced computational complexity and lower power consumption compared to full-precision multiplication.
Solution Approach 2:
The invention changes the parameter of approximation level by dynamically adjusting how many mantissa bits are processed accurately versus approximately. By varying the number of bits processed in different approximation stages, the system can adapt the calculation accuracy to match the specific application requirements, thereby optimizing the trade-off between power consumption and calculation accuracy.
2Device complexity
If fixed logic design is used for approximate multipliers, then circuit complexity is reduced, but accuracy adjustment capability is lost
Solution Approach 1:
The invention introduces dynamic control signals that enable or disable specific approximation stages based on the required accuracy level. This dynamic capability allows the same hardware circuit to operate at different accuracy levels by selectively activating approximation modules, providing adaptability without significantly increasing circuit complexity.
Solution Approach 2:
The approximate multiplier design incorporates universal approximation modules that can handle different bit-width inputs and accuracy requirements using the same core logic structure. The error correction modules are designed to work across multiple approximation levels, making the circuit versatile for various application scenarios while maintaining relatively simple logic design.
3Area of stationary object
If linear iteration method is used for approximation, then area is reduced and speed is increased, but theoretical optimization capability is limited
Solution Approach 1:
The invention implements feedback mechanisms where error terms from each approximation stage are fed into subsequent correction stages. The error correction modules use the output errors from previous stages to generate correction terms, creating a feedback loop that systematically reduces approximation errors. This feedback-based error correction provides a theoretical framework for optimizing the approximation process while maintaining area efficiency and high speed.
Data Source
AI summary
The present invention discloses an error unbiased approximate multiplier for normalized floating-point numbers and an implementation method of the error unbiased approximate multiplier. The error unbiased approximate multiplier includes a symbol and exponent bit module, a mantissa approximation module and a normalization module, wherein the symbol and exponent bit module processes symbolic operation and exponent bit operation of the floating-point numbers; the mantissa approximation module obtains a mantissa approximation result under different accuracy requirements by summing a result of multilevel error correction modules; and the normalization module adjusts an exponent bit according to the operation result of the mantissa and processes the overflow of the exponent bit to obtain the final product result. According to the present invention, for the multiply operation of the normalized floating-point numbers under the IEEE 754 standard, under the controllable accuracy levels, error distribution is unbiased, and area, speed and energy efficiency are obviously improved.