ESC Embedded Diode Assembly for High-Temperature Thermal Stress Relief
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Solution Overview
Problem
Existing diode designs in electrostatic chucks (ESC) for plasma processing chambers fail prematurely due to excessive thermal stress and fatigue at high temperatures, limiting the operating range and reliability for emerging etch processes.
Innovation Solution
The design incorporates a thin plate with an intermediate coefficient of thermal expansion between the silicon diode and the metal strap connector, and uses optimized metal strap connectors with acute angles and epoxy or silicone encapsulation to reduce thermal stress, along with wire bonding alternatives, to enhance diode durability and temperature handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal strap connector is used to connect the silicon diode, then electrical connection is achieved, but thermal stress and fatigue occur due to coefficient of thermal expansion mismatch at high temperatures
Solution Approach 1:
An intermediate layer of electrically conducting material with a second coefficient of thermal expansion is introduced between the silicon diode and the metal strap connector. This intermediate layer acts as a thermal expansion buffer, with its CTE being greater than that of silicon but less than or equal to that of the metal strap connector, thereby reducing thermal stress and preventing solder joint failure at high temperatures.
2Reliability
If the metal strap connector is made more flexible to reduce thermal stress, then thermal fatigue is reduced, but mechanical strength and electrical contact reliability may be compromised
Solution Approach 1:
The metal strap connector is designed with a thin plate configuration that provides flexibility to accommodate thermal expansion differences. The thin plate structure can bend and deform elastically during thermal cycling, reducing thermal fatigue stress on the solder joints while maintaining sufficient mechanical strength and electrical conductivity for reliable operation.
3Reliability
If the diode assembly is encapsulated to protect from environmental factors, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent specifies particular material properties for the encapsulant, requiring it to have an appropriate coefficient of thermal expansion match with the diode assembly and specific dielectric properties. By selecting materials with matched CTE parameters, the encapsulant protects the diode from environmental factors while minimizing thermal stress, and the standardized material selection keeps manufacturing complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These designs significantly extend the operating temperature range and lifetime of the diodes, ensuring reliable ESC performance for high-temperature processes without compromising cost or manufacturing complexity.
Implementation Method 1
having a coefficient of thermal expansion between that of the silicon diode and the metal strap connector
Implementation Method 2
The intermediate layer is bonded to the silicon diode and the metal strap connector with solder material
Data Source
AI summary
A substrate support for a plasma chamber includes a base plate arranged along a plane, a first layer of an electrically insulating material arranged on the base plate along the plane, a plurality of heating elements arranged in the first layer along the plane, and a plurality of diodes arranged in respective cavities in the first layer. The plurality of diodes are connected in series to the plurality of heating elements, respectively. Each of the plurality of diodes includes a die of a semiconductor material arranged in a respective one of the cavities. The semiconductor material has a first coefficient of thermal expansion. A first side of the die is arranged on the first layer along the plane. A first terminal of the die is connected to a first electrical contact on the first layer.


