ESD Analysis Tool for Full Chip Effective Resistance Screening

Solution Overview

Problem

Conventional EDA tools face challenges in efficiently analyzing integrated circuit (IC) designs for potential electrostatic discharge (ESD) instance failures, requiring excessive computational resources and time due to the high number of instances and components involved, which can lead to unreliable and resource-intensive brute force methods.

Innovation Solution

The proposed solution involves performing shorted effective resistance analyses using fast-pairwise algorithms and sparse inverse matrix computations, specifically through B2I and C2I analyses, to efficiently identify potential ESD violations by computing effective resistances between instances, bumps, and ESD protection devices, focusing on top failure instances rather than exact values to reduce computational complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional EDA tools perform brute force analysis of all instances for ESD protection, then comprehensive ESD coverage is achieved, but computational resources and time consumption increase excessively

Engineering Contradiction:

ImproveESD protection coverageVSAvoidanalysis time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the full chip design into multiple analysis phases: initial screening phase using simplified models to identify potential failure instances, and detailed analysis phase for only those identified instances. This segmentation reduces the overall computational burden by avoiding detailed analysis of all instances while maintaining comprehensive ESD protection coverage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by performing detailed effective resistance analysis only on a subset of instances identified as potential failures in the initial screening, rather than analyzing all instances. This approach achieves sufficient ESD protection coverage with reduced computational resources and time.

Inventive Principle:

Principle #16Partial or excessive action

2Reliability

If conventional EDA tools perform brute force analysis of all instances for ESD protection, then comprehensive ESD coverage is achieved, but computational resources and time consumption increase excessively

Engineering Contradiction:

ImproveESD protection coverageVSAvoidcomputational resources

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the full chip design into multiple analysis phases: initial screening phase using simplified models to identify potential failure instances, and detailed analysis phase for only those identified instances. This segmentation reduces the overall computational burden by avoiding detailed analysis of all instances while maintaining comprehensive ESD protection coverage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by performing detailed effective resistance analysis only on a subset of instances identified as potential failures in the initial screening, rather than analyzing all instances. This approach achieves sufficient ESD protection coverage with reduced computational resources and time.

Inventive Principle:

Principle #16Partial or excessive action

3Measurement precision

If detailed effective resistance analysis is performed for all instances, then precise ESD violation detection is achieved, but device complexity and computational load increase

Engineering Contradiction:

ImproveESD violation detection accuracyVSAvoidanalysis complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary screening using simplified resistance models and heuristics to identify potential ESD failure instances before conducting detailed effective resistance analysis. This preliminary action filters out instances that are unlikely to fail, allowing detailed analysis to be focused only on critical cases where high precision is necessary.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies different levels of analysis complexity to different instances based on their risk profile. Instances identified as high-risk through preliminary screening receive detailed effective resistance analysis, while low-risk instances are assessed using simplified models, optimizing the balance between detection accuracy and analytical complexity.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10552564B1Determining worst potential failure instances using full chip ESD analysis

Publication Date: 2020.02.04 CADENCE DESIGN SYST INC

AI summary

In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to techniques for analyzing a design for potential ESD instance failures. Embodiments allow for efficiently determining a potential ESD violation or non-violation status for a large number of instances, such as all the instances in a full chip design, by performing effective resistance analyses between all the instances and all the bumps and ESD protection devices in the design. These and other embodiments further allow for more detailed effective resistance analyses to be performed for potential failing instances.