ESD Protection Layout With Barrier Openings Against Current Crowding

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Solution Overview

Problem

MOS transistor devices with P-type barrier regions are prone to current crowding and hard breakdown when used as ESD protection devices, which affects their protection capability.

Innovation Solution

An ESD protection device is designed with a P-type substrate, including a first and second transistor, an N-type drift region, and a P-type barrier region, where the P-type barrier region has an overlapping portion with the N-type drift region and at least one opening, enhancing the ESD current path and uniformity to prevent current crowding and improve robustness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a P-type barrier region is used to increase breakdown voltage, then the breakdown voltage is improved, but current crowding effect occurs causing hard breakdown

Engineering Contradiction:
Improvebreakdown voltageVSAvoidESD protection capability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The P-type barrier region is segmented by introducing openings (holes) within it, dividing the continuous barrier into separate segments. This segmentation allows current to distribute more uniformly across the barrier region rather than concentrating at specific points, thereby eliminating the current crowding effect while maintaining the breakdown voltage enhancement

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The barrier region is given different local properties by introducing openings at specific locations. The areas with openings have different electrical characteristics compared to the solid barrier regions, creating localized current pathways that prevent current crowding while maintaining overall barrier functionality

Inventive Principle:
Principle #3Local quality

2Reliability

If the ESD current path is increased to prevent current crowding, then the ESD robustness is improved, but the device area may increase

Engineering Contradiction:
ImproveESD robustnessVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The solution addresses current distribution by transitioning from a two-dimensional surface view to a three-dimensional structure. The openings extend vertically through the P-type barrier region, creating current pathways in the vertical dimension rather than requiring horizontal expansion, thus increasing ESD current path without increasing device area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents current crowding and delays hard breakdown while maintaining a compact design, reducing manufacturing complexity and cost by avoiding extra masks and ion implantation processes.

Implementation Method 1

an electrostatic discharge (ESD) protection device

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Data Source

PatentUS20230411382A1Electrostatic discharge protection device
Publication Date: 2023.12.21 POWERCHIP SEMICON MFG CORP
  • US20230411382A1 patent drawing
  • US20230411382A1 patent drawing
  • US20230411382A1 patent drawing

AI summary

An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.