ESD Circuit Trigger Voltage Reduction via Doping Profiles
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Solution Overview
Problem
Existing electrostatic discharge circuits often have high trigger voltages, leading to potential damage to semiconductor circuits, and low holding voltages can result in malfunction and latch-up phenomena, compromising the stability of the discharge process.
Innovation Solution
The electrostatic discharge circuit design includes specific doping regions and layers, such as N+ and P-type regions, epitaxial layers, and buried layers, along with transistors and resistors, to stabilize trigger and holding voltages, reducing resistance and avalanche breakdown voltage, and enhancing discharge capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the trigger voltage is high, then the electrostatic discharge circuit can maintain stable operation, but the semiconductor circuit elements may be damaged or broken before ESD is performed
Solution Approach 1:
The patent modifies the electrical parameters of the electrostatic discharge circuit by adjusting the doping concentrations and spatial distribution of P-type and N-type regions. Specifically, the P-type region is positioned closer to the N+ region than the N-well, and the doping concentration in the P-type region is optimized to reduce the trigger voltage to a safe level that prevents damage to semiconductor circuit elements while maintaining circuit stability
2Productivity
If the holding voltage is low, then the electrostatic discharge circuit can effectively discharge, but the semiconductor circuit may malfunction and latch-up phenomenon may occur
Solution Approach 1:
The patent optimizes the holding voltage by controlling the doping concentration and spatial distribution of the N-well and P-type region. The N-well is positioned at a specific distance from the P-type region, and its doping concentration is adjusted to maintain the holding voltage within an optimal range that enables effective discharge while preventing semiconductor circuit malfunction and latch-up phenomena
3Reliability
If the resistance is high, then the electrostatic discharge circuit can maintain voltage stability, but the breaking current is reduced and discharge effectiveness is compromised
Solution Approach 1:
The patent balances resistance and breaking current by optimizing the doping concentration profile across different regions. The P-type region has a specific doping concentration that provides sufficient resistance for voltage stability, while the N+ region and N-well are doped at concentrations that maintain low resistance paths for high breaking current, thereby achieving both voltage stability and effective discharge
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a lower trigger voltage, higher holding voltage, and increased breaking current, ensuring more stable and effective electrostatic discharge operations compared to traditional circuits.
Implementation Method 1
forming an N+ buried layer in a substrate, forming an n-type epitaxial layer on the N+ buried layer and the substrate, forming an N-well by doping n type ions in a cathode region of the n-type epitaxial layer, forming a first P− region and a second P− region by doping p type ions on an anode region of the n-type epitaxial layer and a portion region of the N-well, forming a first N− region by doping n type ions on another region of the N-well, forming a first N+ region and a second N+ region by doping n type ions on some regions corresponding to a center of the first P− region and some regions of the first N− region, and forming a first P+ region by doping p type ions on some regions of the second P− region
Implementation Method 2
reducing resistance and avalanche breakdown voltage, and enhancing discharge capabilities
Data Source
AI summary
An electrostatic discharge circuit may include a substrate, an N+ buried layer in the substrate, an n-type epitaxial layer on the N+ buried layer and the substrate, a first P− region in an anode region of the n-type epitaxial layer, a first N+ region in the first P− region, an N-well in a cathode region of the n-type epitaxial layer, a first P+ region in the N-well, and a second N+ region located in the N-well. The first N+ region may be located closer to the second N+ region than the first P+ region.