ESD Protection Circuit With Substrate Control to Prevent Latch-Up
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Solution Overview
Problem
Existing electrostatic discharge (ESD) protection circuits are prone to latch-up effects, which can cause chip failure or burning due to parasitic thyristor structures being triggered by external interference, noise coupling, or voltage overshoot, leading to a continuous current amplification loop between power supply and ground.
Innovation Solution
An ESD protection circuit with a trigger unit and a discharge transistor, where the trigger unit generates a signal upon detecting an electrostatic pulse, triggering the discharge transistor to pull the substrate voltage to a level that prevents parasitic transistors from turning on, thereby reducing the risk of latch-up by managing the voltage at the substrate terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ESD protection circuit is provided to discharge electrostatic charges, then chip protection from electrostatic damage is improved, but the circuit is prone to latch-up effects that can cause chip failure
Solution Approach 1:
A control transistor is introduced as an intermediary between the ESD protection circuit and the substrate. This control transistor mediates the voltage at the substrate terminal of the discharge transistor, preventing parasitic transistors from turning on and avoiding latch-up effects while maintaining ESD protection functionality
Solution Approach 2:
The control transistor creates a feedback mechanism where the voltage at the substrate terminal is actively regulated. When electrostatic discharge occurs, the control transistor adjusts the substrate voltage to prevent parasitic transistor activation, providing negative feedback that suppresses latch-up conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces the risk of latch-up effects by ensuring the discharge transistor is triggered to discharge electrostatic charges, maintaining a voltage that prevents parasitic transistors from being activated, thus enhancing chip reliability and preventing damage from electrostatic discharges.
Implementation Method 1
configured to discharge an electrostatic charge to the second pad when triggered the trigger signal
Data Source
AI summary
The present disclosure provides an electrostatic discharge protection circuit, a chip including a first pad and a second pad. The electrostatic discharge protection circuit includes a trigger unit and a discharge transistor. The trigger unit is connected between the first pad and the second pad, provided with a trigger terminal, and configured to generate a trigger signal when there is an electrostatic pulse on the first pad. The first pad is connected to a first voltage, the second pad is connected to a second voltage, and the first voltage is greater than the second voltage. The discharge transistor has a first terminal connected to the first pad, and a second terminal connected to the second pad, and discharges an electrostatic charge to the second pad when triggered by the trigger signal.