3D ESD Protection Circuit Layout for Low Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-frequency applications such as USB 3.1 or 4, HDMI, and Thunderbolt interfaces face challenges in electrostatic discharge protection due to increased parasitic capacitance from ESD protection circuits, which can damage integrated circuits and affect signal integrity.
Innovation Solution
The method involves forming an antiparallel silicon controlled rectifier (SCR) ESD protection circuit with semiconductor devices on a semiconductor substrate, where the first ESD protection device is coupled to a second ESD protection device via a metal connection, and the substrate is thinned to reduce parasitic capacitance, with contact pads formed during front-side processing and metal connections during back-side processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuit is designed with low intrinsic resistance to shunt electrostatic discharges effectively, then electrostatic discharge protection is improved, but parasitic capacitance increases which degrades signal integrity in high-frequency applications
Solution Approach 1:
The patent transitions from planar ESD protection structure to a three-dimensional stacked configuration where ESD protection devices are arranged vertically above each other on the semiconductor substrate. This vertical stacking allows the ESD protection circuit to achieve low intrinsic resistance through multiple parallel protection paths while minimizing the horizontal footprint and reducing parasitic capacitance to signal lines, thus resolving the contradiction between effective ESD protection and signal integrity in high-frequency applications
Solution Approach 2:
The ESD protection circuit is divided into multiple discrete ESD protection devices stacked vertically, with each device providing independent protection functionality. This segmentation allows the total protection capability to be distributed across multiple smaller units, reducing the overall parasitic capacitance while maintaining low intrinsic resistance through parallel connection of the segmented protection paths
Data Source
AI summary
In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.