ESD Protection Circuit for Low-Capacitance Data Output Transistors
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Solution Overview
Problem
Downscaling the size of a protection diode in a semiconductor device without additional measures can lead to a high voltage applied on the output transistor, risking breakdown of the gate insulating film during an ESD test, particularly in CDM mode.
Innovation Solution
Incorporating an ESD protection diode in parallel with the output transistor and optimizing the resistance values of the resistance elements, along with using thicker gate insulating films for certain transistors, to manage current flow and prevent insulation breakdown during ESD tests, allowing for downscaled diode sizes that reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of the protection diode is downscaled to decrease parasitic capacitance, then signal quality is improved, but voltage applied on the output transistor increases causing gate insulating film breakdown
Solution Approach 1:
A first resistance element is introduced as an intermediary component between the data I/O terminal and the output transistor. This resistance element limits the current flow during ESD events, preventing excessive voltage from reaching the output transistor while allowing the protection diode to be downscaled for lower parasitic capacitance. The resistance element acts as a buffer that mediates between the ESD protection function and the signal transmission quality requirements.
Solution Approach 2:
The patent changes the electrical parameters of the protection circuit by introducing a resistance element with specific resistance value. This parameter change allows the circuit to maintain ESD protection capability while enabling the protection diode to operate at a smaller size with lower capacitance. The resistance value is carefully selected to balance ESD protection requirements with signal quality requirements during normal operation.
2Productivity
If the protection diode size is reduced to lower parasitic capacitance, then data transmission performance is improved, but ESD protection capability deteriorates
Solution Approach 1:
The resistance element serves as a mediator that compensates for the reduced ESD protection capability of the downscaled protection diode. By placing the resistance element in series with the output transistor, it limits the current during ESD events, effectively making up for the smaller diode's reduced protection capability while maintaining the benefits of lower parasitic capacitance.
Solution Approach 2:
The ESD protection function is segmented into two parts: the protection diode for clamping voltage and the resistance element for current limiting. This segmentation allows each component to be optimized independently - the diode can be small for low capacitance while the resistance element provides the necessary current limiting for adequate ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents insulation breakdown of the output transistor during ESD tests, enabling downscaled diode sizes that improve signal quality by reducing parasitic capacitance, thus enhancing the performance of read and write data operations.
Implementation Method 1
a first ESD protection diode is connected between a data I/O terminal and a power line
Implementation Method 2
a first resistance element is connected between the data I/O terminal and a source or a drain of the output transistor
Implementation Method 3
using thicker gate insulating films for certain transistors, to manage current flow and prevent insulation breakdown during ESD tests
Data Source
AI summary
An example apparatus includes a data terminal, a first power line supplied with a first voltage, a second power line supplied with a second voltage different from the first voltage, first and second transistors coupled in series between the first power line and the data terminal, a third transistor coupled between the second power line and the data terminal, and a first ESD protection element coupled between the first power line and a first internal node between the first and second transistors.