ESD Protection Circuit Sizing for RF Voltage Spike Suppression

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Solution Overview

Problem

Existing semiconductor devices face challenges in effectively protecting against electrostatic discharge (ESD), particularly in suppressing voltage rises and drops, which can damage the devices and affect their performance in radio-frequency signal amplification.

Innovation Solution

A semiconductor system with a protective device configuration that includes diodes, transistors, and a resistor, where the transistors are sized differently to manage ESD by quickly switching states and using diodes to function as discharge paths, effectively suppressing voltage peaks and drops.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a protective device is added to suppress ESD, then ESD susceptibility is improved, but device complexity increases

Engineering Contradiction:
ImproveESD susceptibilityVSAvoidprotective device configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protective device is segmented into multiple functional components: a first protective circuit for voltage rise protection, a second protective circuit for voltage drop protection, and a third protective circuit for reverse current protection. Each segment handles a specific aspect of ESD protection, allowing the system to achieve comprehensive protection while maintaining modularity and reducing overall complexity through functional decomposition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protective circuits are designed to activate before ESD damage can occur. The first protective circuit preemptively clamps voltage rises, the second protective circuit preemptively addresses voltage drops, and the third protective circuit preemptively blocks reverse currents. This preliminary action prevents ESD effects from propagating to sensitive components, achieving reliable protection without requiring complex real-time response systems.

Inventive Principle:
Principle #10Preliminary action

2Speed

If transistors are sized differently to quickly switch states, then ESD suppression speed is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvetransistor switching speedVSAvoidtransistor sizing precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

Different transistor sizes are assigned to different positions within the protective circuits based on their specific functional requirements. The first protective circuit uses transistors sized for optimal voltage rise suppression speed, the second protective circuit uses transistors sized for optimal voltage drop suppression speed, and the third protective circuit uses transistors sized for optimal reverse current blocking speed. This local quality approach allows each transistor to be optimized for its specific role, achieving high overall switching speed while making manufacturing precision requirements manageable through localized optimization rather than uniform high precision across all components.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The semiconductor system improves ESD susceptibility by reducing inrush current and peak voltage, while maintaining a compact design and efficient radio-frequency signal amplification capabilities.

Implementation Method 1

ESD is a static discharge, and is a phenomenon in which a large current instantaneously flows between two objects at different potentials. When an ESD occurs, a current flows from an object at a high potential to an object at a low potential.

Methodology Applied
Scientific EffectElectrostatic Discharge: Electrostatic Discharge

Data Source

PatentUS12142604B2Semiconductor device and semiconductor system including electro static discharge (ESD) protective device
Publication Date: 2024.11.12 KK TOSHIBA
  • US12142604B2 patent drawing
  • US12142604B2 patent drawing
  • US12142604B2 patent drawing

AI summary

According to one embodiment, a first P-type transistor with a gate is coupled to a first node, and a drain is coupled to a second node. A first N-type transistor with a gate is coupled to the first node, and a drain is coupled to the second node. A second P-type transistor with a gate is coupled to the second node, and a drain is coupled to a third node. A second N-type transistor with a gate is coupled to the second node, and a drain is coupled to the third node. The first P-type transistor is smaller than the first N-type transistor. The second N-type transistor is smaller than the second P-type transistor. The second N-type transistor is smaller than the first N-type transistor.