ESD Discharge Circuit With Voltage-Boosted Stable Triggering
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Solution Overview
Problem
Electrostatic discharge (ESD) can cause permanent damage to electronic components and integrated circuits, and existing protection circuits often struggle with stability and effectiveness during manufacturing, packaging, testing, storage, and transportation.
Innovation Solution
An electrostatic discharge circuit with a stable discharging mechanism, comprising a voltage-dividing circuit, inverters, a voltage boosting circuit, an RC circuit, and an ESD transistor, which directly detects voltage variations to ensure quick and stable discharging operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing protection circuits are used, then electrostatic discharge protection is provided, but the discharging mechanism is unstable and ineffective
Solution Approach 1:
The protection circuit is divided into multiple functional modules: voltage detection module (first voltage-dividing circuit), voltage boosting module (first voltage boosting circuit), control module (second voltage-dividing circuit and second inverter), and discharge module (ESD transistor). Each module performs a specific function in the discharge process, improving overall reliability through functional segmentation.
Solution Approach 2:
The patent introduces intermediate circuits between the ESD transistor and power input terminal, including voltage detection circuits, voltage boosting circuits, and control circuits. These intermediary circuits process and control the discharge process, ensuring stable and effective protection against ESD damage.
2Speed
If direct voltage detection is used, then quick response is achieved, but discharging time is insufficient for stable operation
Solution Approach 1:
The first voltage-dividing circuit detects voltage variations in advance and triggers the voltage boosting circuit to prepare the discharge condition. This preliminary detection and preparation ensures quick response while maintaining sufficient discharge duration for stable operation.
Solution Approach 2:
The circuit employs periodic voltage detection and boosting cycles through the inverters and voltage-dividing circuits, creating a controlled oscillating discharge pattern that maintains both quick response and sufficient discharge duration for stable operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit achieves a stable and effective discharging mechanism, ensuring the protection of electronic components from ESD damage while maintaining a long enough discharging time for stable operation.
Implementation Method 1
a voltage-dividing circuit electrically coupled to a voltage input terminal configured to receive a power signal, so as to generate a detection signal at a voltage-dividing terminal
Implementation Method 2
a first inverter configured to receive and invert the detection signal to output an inverted detection signal
Implementation Method 3
The voltage boosting circuit includes a first PMOS circuit, a first NMOS circuit and a second NMOS circuit
Implementation Method 4
a resistive circuit for providing resistance that is electrically coupled between the voltage input terminal and a control terminal and a capacitive circuit for providing capacitance that is electrically coupled between the control terminal and a ground terminal
Implementation Method 5
The electrostatic discharge transistor is electrically coupled between the voltage input terminal and the ground terminal and configured to be controlled by the boosted detection signal for performing discharging on the voltage input terminal
Data Source
AI summary
The present invention discloses an electrical discharge circuit having stable discharging mechanism. A voltage-dividing circuit generates a detection signal such that a first inverter outputs an inverted detection signal. A first PMOS and a first NMOS are coupled through a first terminal between the voltage input terminal and a ground terminal. A second NMOS is coupled between a second terminal and the ground terminal. A first PMOS control terminal is coupled to the second terminal. A first and a second NMOS control terminals respectively receive the inverted detection signal and the detection signal. A resistor and a capacitor are coupled through the control terminal coupled to the second terminal and between the voltage input terminal and the ground terminal. A second inverter receives an inverted boosted detection signal from the control terminal to output a boosted detection signal to control an electrostatic discharge MOS to discharge the voltage input terminal.