ESD Clamp Trigger Voltage Consistency via Base-Collector Spacing

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Solution Overview

Problem

Existing electrostatic discharge (ESD) clamps in semiconductor devices face challenges due to variations in base-collector spacing dimension, leading to inconsistent trigger voltages and increased manufacturing costs, especially when cascaded to achieve higher trigger voltages, which affects overall yield and current handling capabilities.

Innovation Solution

The implementation of ESD clamps with transistors having base-collector spacing dimensions chosen from specific zones (Z1, Z2, Z3) to minimize sensitivity to spacing variations, allowing for cascaded stacks to achieve higher trigger voltages while maintaining consistent operation across different regions and manufacturing lots without significant process modifications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If base-collector spacing dimension is increased to achieve higher trigger voltages, then trigger voltage capability is improved, but sensitivity to spacing variations increases leading to inconsistent operation

Engineering Contradiction:
Improvetrigger voltage capabilityVSAvoidoperation consistency
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies parameter changes by selecting base-collector spacing dimensions from specific zones (Z1, Z2, Z3) where the sensitivity to spacing variations is minimized. This transforms the continuous parameter of base-collector spacing into discrete optimal values that achieve higher trigger voltages while maintaining consistent operation across manufacturing variations.

Inventive Principle:
Principle #35Parameter changes

2Power

If cascaded stacks are implemented to achieve higher trigger voltages, then voltage capability is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvetrigger voltage capabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

Instead of increasing device complexity through cascaded stacks, the patent changes the parameter of base-collector spacing dimension to specific zone values. This allows achieving higher trigger voltages through parameter optimization rather than structural complexity, thereby reducing manufacturing complexity and cost.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If base-collector spacing dimension varies, then manufacturing flexibility is improved, but trigger voltage consistency deteriorates

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidtrigger voltage consistency
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent resolves this contradiction by identifying specific zones (Z1, Z2, Z3) of base-collector spacing dimensions where manufacturing flexibility is maintained but trigger voltage consistency is improved. By selecting spacing dimensions from these zones, the patent achieves both manufacturing flexibility and precise trigger voltage control.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the sensitivity of stacked ESD devices to spacing variations, enabling a wide range of trigger voltages with reduced manufacturing complexity and increased current handling capabilities, thus enhancing the reliability and efficiency of ESD protection in semiconductor devices.

Implementation Method 1

When the voltage across terminals 22, 23 rises beyond a predetermined limit, bipolar transistor 25 turns on, limiting the voltage across terminals 22, 23

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS9018071B2Methods for forming electrostatic discharge protection clamps with increased current capabilities
Publication Date: 2015.04.28 NXP USA INC
  • US9018071B2 patent drawing
  • US9018071B2 patent drawing
  • US9018071B2 patent drawing

AI summary

Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1<Rbe<800 Ohms.