ESD Clamp Parallel to Blocking Capacitor in RF Switching Circuit

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Solution Overview

Problem

Integrated circuits (ICs) face challenges in protecting against electrostatic discharge (ESD) during fabrication and operation, as traditional ESD protection methods can compromise reliability and performance, and increase the footprint of ICs.

Innovation Solution

An electronic switching circuit is designed with ESD clamps disposed in parallel to blocking capacitor elements, providing a low-impedance discharging path around the capacitors, minimizing parasitic effects and improving performance and reliability, especially for high-power switching circuits like RF switching circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If traditional ESD protection methods are used, then ESD protection is provided, but reliability and performance are compromised and footprint increases

Engineering Contradiction:
ImproveESD protectionVSAvoidcircuit reliability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

An ESD clamp circuit is introduced as an intermediary component connected in parallel with the blocking capacitor. This clamp circuit acts as a mediator that provides a safe discharge path for ESD events while isolating the blocking capacitor from direct ESD stress, thereby protecting the main circuit while maintaining reliability and performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If ESD clamp is added to provide protection, then ESD discharging capability is improved, but parasitic effects increase

Engineering Contradiction:
ImproveESD discharging capabilityVSAvoidparasitic effects
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The ESD clamp circuit is designed with locally optimized characteristics - using specific transistor configurations and component values that minimize parasitic capacitance and inductance in the ESD discharge path. The clamp is engineered to have low parasitic effects only where needed for ESD protection, while maintaining high quality factors for the blocking capacitors in the signal path.

Inventive Principle:
Principle #3Local quality

3Object-affected harmful factors

If ESD clamp is disposed in parallel to blocking capacitor, then ESD discharging path is provided, but circuit complexity increases

Engineering Contradiction:
ImproveESD discharging pathVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The ESD clamp circuit is merged with the existing blocking capacitor structure by connecting them in parallel at the same nodes. This integration allows the ESD protection function to be added without requiring separate discrete components or additional connection points, thereby minimizing the increase in circuit complexity while still providing effective ESD discharge capability.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively discharges ESD events without impacting normal operations, enhancing the reliability and performance of electronic switching circuits while minimizing footprint and parasitic effects.

Implementation Method 1

an ESD clamp is disposed in parallel to the blocking capacitor element to provide a low-impedance ESD discharging path around the blocking capacitor element

Methodology Applied
Scientific EffectElectrostatic Discharge: Electrostatic Discharge

Data Source

PatentUS10354994B2Electrostatic discharge (ESD) protection in an electronic switching circuit
Publication Date: 2019.07.16 QORVO US INC
  • US10354994B2 patent drawing
  • US10354994B2 patent drawing
  • US10354994B2 patent drawing

AI summary

Aspects disclosed herein include electrostatic discharge (ESD) protection in an electronic switching circuit. An electronic switching circuit includes switching circuitry configured to provide interconnectivity between a common port in at least one common branch and an input/output (I/O) port in at least one I/O branch. The common branch and the I/O branch each include a blocking capacitor element that is inherently incapable for ESD discharging. As such, an ESD clamp is disposed in parallel to the blocking capacitor element to provide a low-impedance ESD discharging path around the blocking capacitor element. By disposing the ESD clamp in parallel to the blocking capacitor element, it is possible to minimize detrimental parasitic effects of the ESD clamp, thus improving performance and reliability of the electronic switching circuit, especially for high power switching circuits such as a radio frequency (RF) switching circuits.