ESD Clamp Topology With Diode Feedback for Low Leakage
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Solution Overview
Problem
Electrostatic discharge (ESD) clamps using large n-type field-effect transistors (FETs) experience parasitic leakage currents that are temperature- and voltage-dependent, posing challenges for stringent sleep current and low-power specifications in RF applications.
Innovation Solution
A clamping circuit comprising a field-effect transistor, a diode, and coupling circuitry that includes an RC network and an inverter, with a diode network situated between the voltage source and the FET to reduce leakage current, and a diode placed between the FET and a ground node to create a DC feedback mechanism, minimizing leakage and enhancing ESD compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large n-type FETs are used in ESD clamps, then ESD protection capability is improved, but parasitic leakage current increases
Solution Approach 1:
The patent divides the ESD clamp into multiple FETs connected in series, where each FET operates at a lower voltage stress. This segmentation reduces the parasitic leakage current of individual devices while maintaining the overall ESD protection capability through the series configuration.
Solution Approach 2:
The patent introduces intermediate voltage nodes between series-connected FETs, which act as mediators to distribute voltage stress and reduce the leakage current. These intermediate nodes allow each FET to operate at lower voltage, thereby reducing parasitic effects while maintaining total ESD protection.
2Reliability
If FET size is increased to handle higher ESD currents, then ESD compliance is improved, but sleep current specification becomes harder to meet
Solution Approach 1:
The patent segments the large FET into multiple smaller FETs connected in series. Each smaller FET has reduced parasitic leakage, which directly addresses the sleep current specification while the series combination maintains the ability to handle high ESD currents.
Solution Approach 2:
The patent changes the voltage distribution parameter across the FETs by introducing intermediate nodes, allowing each device to operate at lower voltage stress. This parameter change reduces the leakage current exponential dependence on voltage while maintaining overall ESD protection capability.
3Loss of energy
If series-connected FETs are used to reduce leakage, then parasitic leakage current is reduced, but device complexity increases
Solution Approach 1:
The intermediate voltage nodes introduced in the series FET configuration serve multiple functions: they reduce leakage current by distributing voltage stress, provides ESD protection at each node, and enable independent biasing of each FET. This multi-functionality justifies the increased device complexity.
Solution Approach 2:
The intermediate nodes act as mediators that simplify the overall system behavior by breaking down the complex large-signal ESD event into manageable smaller events at each node, making the circuit more predictable and easier to design while reducing leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and improves ESD compliance by maintaining the gate-to-source voltage of the FET in the OFF position, allowing for faster response times and reduced risk of damage from voltage spikes, while maintaining minimal added components and optimal ESD protection.
Implementation Method 1
a diode placed between the FET and a ground node to create a DC feedback mechanism, minimizing leakage
Implementation Method 2
Electrostatic discharge (ESD) clamps that use large n-type FETs (nFETs) have parasitic leakage current that are temperature and voltage dependent
Implementation Method 3
maintaining the gate-to-source voltage of the FET in the OFF position, allowing for faster response times
Data Source
AI summary
A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.