ESD Clamp Disable Circuit for Transient EOS Protection
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Solution Overview
Problem
Existing active ESD clamp circuits in semiconductor ICs are vulnerable to transient powered electrical overstress (EOS) voltage events, which can cause damage and render the IC inoperable.
Innovation Solution
An electrostatic discharge (ESD) clamp circuit with a disable circuit that selectively disables the discharge circuit during EOS events, using logic states to control switch operation and prevent current flow during non-ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an active ESD clamp circuit is implemented to protect against ESD events, then ESD protection capability is improved, but vulnerability to transient powered EOS voltage events increases
Solution Approach 1:
The patent implements a dynamic control mechanism that adjusts the state of the discharge circuit based on operating conditions. A control circuit monitors voltage conditions and dynamically switches the discharge circuit between enabled and disabled states, allowing the system to adapt to different scenarios (ESD events vs. EOS events) and avoid damage from harmful voltage transients while maintaining protection when needed.
Solution Approach 2:
The patent introduces a control circuit as an intermediary between the voltage input and the discharge circuit. This control circuit monitors voltage conditions and mediates the activation state of the discharge circuit, enabling selective protection against ESD events while preventing vulnerability to EOS events by disabling the discharge path when appropriate.
2Reliability
If the discharge circuit is always enabled to protect against ESD, then ESD protection is maintained, but damage from transient powered EOS events occurs
Solution Approach 1:
The discharge circuit transitions from a static always-enabled state to a dynamic state controlled by voltage monitoring. The control circuit detects voltage conditions and adjusts the discharge circuit state accordingly, maintaining protection during ESD events while preventing damage during EOS events, thus resolving the contradiction between continuous protection and resistance to harmful events.
Solution Approach 2:
The control circuit performs preliminary detection of voltage conditions before the discharge circuit is activated. By monitoring voltage levels and rates of change in advance, the system can prevent harmful current flow during EOS events by disabling the discharge circuit before damage occurs, while still enabling rapid protection during legitimate ESD events.
3Strength
If a disable circuit is added to selectively disable the discharge circuit, then resistance to EOS events is improved, but device complexity increases
Solution Approach 1:
The control circuit performs multiple functions: it monitors voltage conditions, detects ESD events, detects EOS events, and controls the discharge circuit state. By consolidating these functions into a single multi-functional control block, the patent minimizes the increase in device complexity while achieving the goal of selective discharge circuit disabling for EOS protection.
Solution Approach 2:
The patent combines the ESD detection functionality and the disable control functionality into an integrated control circuit. This merging of functions reduces the overall complexity compared to having separate independent circuits for each function, while still providing the necessary selective disabling capability to protect against EOS events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Protects the ESD clamp circuit from damage during EOS events while maintaining functionality during normal operation, ensuring the IC's integrity and performance.
Implementation Method 1
a disable circuit coupled between the discharge circuit and the disable input to disable the discharge circuit, wherein the disable circuit includes a second switch. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.
Implementation Method 2
a discharge circuit to discharge a current flow during a transient ESD voltage event
Implementation Method 3
the active ESD clamp circuit is turned on and provides a pathway between the input to ground for the ESD-induced current to flow so that the current is diverted away from the protected circuits in the IC
Data Source
AI summary
A system and method for an electrostatic discharge (ESD) clamp circuit containing a disable circuit to selectively disable a discharge circuit is disclosed. An electrostatic discharge (ESD) clamp circuit including a discharge circuit to discharge a current flow during a transient ESD voltage event; a disable input to receive a disable input signal; and a disable circuit to, based upon the disable input signal, selectively disable the discharge circuit. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.