ESD Clamp Disablement Latch for Power Rail Stability
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Solution Overview
Problem
Existing ESD protection circuits in CMOS integrated circuits are prone to false triggering due to fluctuations in the power supply, leading to power rail instability and recurring oscillations, especially in applications with voltage transients or current-limited power supplies.
Innovation Solution
The implementation of an ESD clamp with a latch mechanism that includes a resistor, capacitor, and field-effect transistors (FETs) to prevent false triggering, where the latch ensures the ESD protection circuit remains off during power glitches by maintaining a logic low level during power-up and charging the capacitor to a threshold level, thereby preventing current sinking from the power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ESD protection circuit uses a simple RC time constant network to control the clamp duration, then the circuit can dissipate ESD pulses effectively, but the circuit becomes sensitive to power supply voltage transients and may false trigger
Solution Approach 1:
A latch circuit is introduced as an intermediary between the RC time constant network and the transistor array. The latch acts as a mediator that filters out spurious voltage transients while allowing genuine ESD events to trigger the protection circuit. The latch requires a sustained voltage threshold exceedance to activate, thereby distinguishing between momentary noise and real ESD pulses.
Solution Approach 2:
The latch circuit is pre-configured with trigger and set inputs that must be simultaneously activated for a sustained period before the transistor array is enabled. This preliminary action requirement ensures that transient voltage spikes are ignored while genuine ESD events that maintain the trigger condition are properly detected and responded to.
2Reliability
If the ESD protection circuit turns on in response to voltage transients, then power rail protection is provided, but the transistor array may stay on indefinitely causing power rail drawdown
Solution Approach 1:
The latch circuit incorporates feedback mechanisms where the trigger input and set input must work together in a specific sequence and duration to activate the protection circuit. This feedback control ensures that the transistor array is only activated when a genuine ESD event is detected, preventing indefinite activation and associated power loss while maintaining protection when needed.
3Reliability
If the ESD clamp activates during power-up due to current limited power supply, then ESD protection is provided, but recurring oscillations occur when the RC time constant releases
Solution Approach 1:
The latch circuit requires sustained activation of both trigger and set inputs before enabling the transistor array. During power-up transients, the voltage fluctuations are insufficient to maintain the trigger condition long enough to activate the latch, preventing spurious activation and subsequent oscillations while still providing protection against genuine ESD events.
Solution Approach 2:
The latch circuit dynamically responds to the duration and magnitude of voltage transients. It adapts its activation threshold based on the sustained nature of the input signal, allowing it to ignore brief power-up fluctuations while responding to prolonged ESD events, thereby maintaining power supply stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents false triggering of the ESD protection circuit, ensuring stable power supply and preventing power rail drawdown by maintaining the ESD clamp off during power glitches and voltage transients, thus enhancing the reliability of integrated circuits.
Implementation Method 1
a resistor-capacitor (RC) time constant network 12 composed of a resistor 14 and a capacitor 16
Implementation Method 2
the transistor array 20 to clamp the power supply to ground during the ESD event
Data Source
AI summary
The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.