ESD Clamp Leakage Reduction via Negative Gate Voltage
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Solution Overview
Problem
RC-triggered power clamps used for ESD protection in handheld devices, such as cellular telephones, are large in size and have high DC leakage, leading to energy loss and battery drainage.
Innovation Solution
The implementation of a structure comprising inverters connected to a timing circuit, with a first and second transistor in series, and a negative voltage source to reduce leakage during normal operations, turning the transistors on during ESD events and off during normal operations to block signals, and applying a negative voltage to the second transistor to minimize leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RC-triggered power clamps are used for ESD protection in handheld devices, then ESD protection is provided, but DC leakage is high causing energy loss and battery drainage
Solution Approach 1:
The patent applies parameter changes by introducing a negative voltage to the gate of the second transistor (M2) during normal operations. This voltage parameter modification reduces the off-state leakage current of the transistor, thereby decreasing DC leakage and energy consumption while maintaining ESD protection capability when needed
2Reliability
If RC-triggered power clamps are used for ESD protection, then ESD protection is achieved, but the device size is large
Solution Approach 1:
The patent merges multiple functions into a single integrated circuit structure. The ESD protection clamp is combined with a timing circuit and inverter logic, allowing the circuit to perform both ESD protection and timing/control functions within a compact footprint, thereby reducing the overall device area while maintaining protection effectiveness
Data Source
AI summary
The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.