ESD Clamp Shallow P-Well Leakage Reduction

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Solution Overview

Problem

Conventional ESD power clamps in high-voltage applications are vulnerable to electrostatic discharge (ESD) transients, which can lead to electrical breakdown and leakage currents due to the formation of inversion layers, resulting in snapback and reduced reliability.

Innovation Solution

The implementation of a Shallow P-well region with a higher p-type impurity concentration between shallow n-well regions in the ESD clamp structure, which reduces the likelihood of inversion layer formation and leakage currents by altering the electrical field and eliminating snapback in Transmission Line Pulse (TLP) curves.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ESD power clamps are implemented using BJTs with HVNW and HVPW regions, then ESD protection is provided, but inversion layers form causing leakage currents and snapback

Engineering Contradiction:
ImproveESD protection reliabilityVSAvoidleakage currents and snapback
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a shallow p-well region with higher p-type impurity concentration specifically in the HVPW region beneath the shallow n-well regions. This localized modification creates a more favorable electrical field distribution in the critical area where inversion layers form, reducing leakage currents and eliminating snapback while maintaining overall ESD protection functionality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies the impurity concentration parameter by introducing a shallow p-well region with higher p-type impurity concentration in the HVPW region. This parameter change alters the electrical field characteristics and reduces the likelihood of inversion layer formation, thereby eliminating snapback and reducing leakage currents.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If shallow n-well regions are formed in HVNW and HVPW regions, then ESD current conduction is enabled, but inversion layer formation occurs leading to reduced performance

Engineering Contradiction:
ImproveESD current conduction capabilityVSAvoidinversion layer formation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The shallow p-well region acts as an intermediary structure between the HVPW region and the shallow n-well regions. It modifies the electrical field distribution in the intermediate region, preventing inversion layer formation while allowing ESD current to conduct through the bipolar transistor structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By introducing the shallow p-well region with higher p-type impurity concentration in the specific location beneath the shallow n-well regions, the patent creates a localized improvement in electrical field distribution that prevents inversion layer formation without affecting the overall ESD current conduction path.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The introduction of the Shallow P-well region effectively reduces leakage currents and eliminates snapback, enhancing the reliability and performance of ESD clamps by maintaining a thinner or eliminating the inversion layer, thereby improving the ESD protection in high-voltage applications.

Implementation Method 1

The shallow p-well region has a p-type impurity concentration higher than a p-type impurity concentration of the HVPW region

Methodology Applied
Scientific EffectImpurity concentration effect:

Implementation Method 2

reduces the likelihood of inversion layer formation and leakage currents by altering the electrical field

Methodology Applied
Scientific EffectElectrical field effect: Electric Field

Data Source

PatentUS8916935B2ESD clamp in integrated circuits
Publication Date: 2014.12.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8916935B2 patent drawing
  • US8916935B2 patent drawing
  • US8916935B2 patent drawing

AI summary

A device includes a High-Voltage N-Well (HVNW) region have a first edge, and a High-Voltage P-Well (HVPW) region having a second edge adjoining the first edge. A first Shallow N-well (SHN) region is disposed over a lower portion of the HVNW region, wherein the first SHN region is spaced apart from the first edge by an upper part of the HVNW region. A second SHN region is disposed over a lower portion of the HVPW region, wherein the second SHN region is laterally spaced apart from the second edge. A Shallow P-well (SHP) region is disposed over the lower portion of the HVPW region, and is between the first SHN region and the second SHN region. The SHP region has a p-type impurity concentration higher than a p-type impurity concentration of the HVPW region. An isolation region is disposed over and contacting the SHP region.