ESD Power Clamp Trigger Circuit Using Low Stress Voltage Devices
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Solution Overview
Problem
Integrated circuits face challenges in accommodating a wide range of power supply voltages and protecting against electrostatic discharge (ESD) due to varying breakdown voltages and the limitations of existing protection circuits, which can lead to circuit failures during high voltage exposure.
Innovation Solution
A protection circuit with a voltage drop network and shunt circuits using low-voltage devices, including an RC trigger stage and NMOS shunt stages, coupled through a PMOS equalization device to provide robust ESD protection across high and low voltage levels, effectively managing excessive supply voltages and ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reverse-biased diodes are used as avalanche breakdown clamps to limit voltage, then high voltage protection is provided, but the breakdown voltage varies widely due to design and fabrication variations
Solution Approach 1:
The patent changes the operating parameter from relying on fixed breakdown voltage to using controllable gate voltage. The ESD protection circuit uses variable voltage control through the gate terminal to adjust the turn-on voltage dynamically, replacing the fixed breakdown characteristic with a controllable parameter that can be precisely set during operation.
Solution Approach 2:
The patent implements feedback control where the voltage at the gate terminal is monitored and adjusted based on the actual voltage conditions. The control circuit responds to voltage changes and adjusts the gate voltage accordingly, creating a closed-loop system that maintains consistent protection characteristics despite manufacturing variations.
2Reliability
If low-voltage devices are used in high-voltage environments, then device stress is reduced, but the devices cannot withstand the full voltage range without protection
Solution Approach 1:
The patent introduces an intermediary ESD protection circuit between the high-voltage environment and the low-voltage devices. This protection circuit acts as a mediator that blocks harmful high voltage transients and ESD events from reaching the sensitive low-voltage devices, while allowing normal operation voltages to pass through.
Solution Approach 2:
The patent provides beforehand protection by placing ESD protection structures at the input terminals before the high voltage can reach the low-voltage devices. The protection circuit is pre-configured to clamp or divert voltage spikes and ESD events, cushioning the vulnerable devices from exposure before damage can occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects low-voltage transistors and circuits from high voltage and ESD events, offering improved ESD tolerance and efficiency by distributing current paths through multiple shunt circuits, scalable to various IC designs without significant size increase.
Implementation Method 1
The RC trigger circuit comprises a capacitor coupled in series to a resistor and a trigger inverter. The resistor and capacitor values are selected to produce an RC time constant that is shorter than an expected rise time for the high voltage rail
Implementation Method 2
A protection circuit with a voltage drop network and shunt circuits using low-voltage devices, including an RC trigger stage and NMOS shunt stages
Implementation Method 3
Present protection circuits typically utilize reverse-biased diodes acting as avalanche breakdown clamps to limit the voltage between the power supply terminals of the IC
Data Source
AI summary
Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.