ESD Clamping Circuit Using Intrinsic Capacitance Triggering
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Solution Overview
Problem
Existing semiconductor switch clamping circuits face challenges in balancing small chip area requirements, low clamping voltage, and preventing activation by high DC voltages while effectively dissipating electrostatic discharges, which are conflicting goals.
Innovation Solution
A clamping circuit design incorporating a first transistor, an amplifier circuit, and a trigger circuit with intrinsic capacitance of a second transistor, allowing dynamic activation by discharge current without the need for large capacitors, enabling efficient ESD protection on a small chip area without static threshold voltage activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional RC trigger circuit with a large capacitor is used to detect ESD events, then the ESD detection capability is improved, but the chip area increases significantly
Solution Approach 1:
The patent extracts the capacitor from the traditional RC trigger circuit and replaces it with the intrinsic capacitance of the second transistor (Q2). This removes the need for a large external capacitor while maintaining the ESD detection function, thereby significantly reducing chip area occupation.
Solution Approach 2:
The second transistor (Q2) serves multiple functions: it acts as part of the amplification stage and simultaneously provides the capacitance needed for ESD event detection through its intrinsic capacitance. This multi-functionality eliminates the need for a dedicated capacitor component.
2Reliability
If the clamping circuit is designed to activate at low voltages to protect against ESD, then ESD protection is improved, but the circuit may incorrectly activate under normal high DC voltage conditions
Solution Approach 1:
The patent employs dynamic triggering based on the rate of change of voltage rather than a static voltage threshold. The intrinsic capacitance of Q2 responds to rapid voltage changes (dV/dt) characteristic of ESD events, allowing the circuit to distinguish between transient ESD pulses and steady-state DC voltages.
Solution Approach 2:
The amplifier circuit provides feedback that enhances the response to rapid voltage changes while suppressing response to steady voltages. The feedback mechanism ensures that only transient ESD events trigger the clamping action, preventing false activation under normal DC operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves efficient ESD protection by dynamically activating the clamping circuit in response to transient electrostatic discharges, reducing chip area usage and avoiding damage from high DC voltages, while maintaining low clamping voltage and small chip area requirements.
Implementation Method 1
at least part of the discharge current drives a control terminal of the second transistor via an intrinsic capacitance of the second transistor
Data Source
AI summary
A clamping circuit for protection against ESD events is described. In accordance with one exemplary embodiment, the circuit comprises the following: a first transistor having a control terminal and a load current path connected between a first contact and a second contact; an amplifier circuit having an amplifier input and an amplifier output connected to the control terminal of the transistor; and a trigger circuit, which is connected between the first contact and the second contact, and comprises a second transistor. The trigger circuit is configured to generate a voltage swing at the amplifier input as a reaction to a discharge current at the first contact by virtue of the fact that at least part of the discharge current drives a control terminal of the second transistor via an intrinsic capacitance of the second transistor.