ESD Protection Circuit with Segmented Clamping and Diode Steering
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Solution Overview
Problem
Current ESD protection circuits in integrated circuits have higher internal resistance due to their design, which reduces their performance in managing electrostatic discharge, particularly because they rely on input/output transistors for voltage endurance, leading to unbalanced discharge speeds for positive and negative ESD currents.
Innovation Solution
The proposed solution involves an electrostatic discharge protection device comprising a first clamping circuit, a second clamping circuit, and a diode circuit, where the first clamping circuit is implemented with core transistors and the second with input/output transistors or stacked core transistors, configured to steer ESD current between power rails with different voltages, thereby reducing internal resistance and enhancing discharge capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuits are implemented by I/O transistors for voltage endurance, then voltage endurance is improved, but internal resistance increases and discharge performance deteriorates
Solution Approach 1:
The ESD protection circuit is divided into two separate clamping circuits: a first clamping circuit implemented with core transistors for low resistance discharge, and a second clamping circuit implemented with I/O transistors for voltage endurance. This segmentation allows each circuit to specialize in its strength without compromise.
Solution Approach 2:
Different parts of the ESD protection system are assigned different transistor types based on their functional requirements. The first clamping circuit uses core transistors optimized for low resistance and high discharge capability, while the second clamping circuit uses I/O transistors optimized for voltage endurance. This local quality differentiation resolves the contradiction between discharge performance and voltage endurance.
2Reliability
If I/O transistors are used for ESD protection, then voltage endurance is improved, but discharge speed becomes unbalanced and performance deteriorates
Solution Approach 1:
The ESD protection function is segmented into two parallel clamping circuits with different transistor implementations. The first clamping circuit using core transistors provides fast discharge speed, while the second clamping circuit using I/O transistors ensures voltage endurance. This segmentation enables both speed and reliability to be optimized simultaneously.
Solution Approach 2:
The invention changes the transistor type parameter from uniform I/O transistors to a combination of core transistors and I/O transistors in different clamping circuits. This parameter change enables optimization of both discharge speed (via core transistors) and voltage endurance (via I/O transistors), resolving the contradiction between speed and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in lower internal resistance and balanced discharge speeds for both positive and negative ESD currents, improving the overall performance of ESD protection devices by utilizing clamping circuits with lower working voltages and reduced internal resistance.
Implementation Method 1
The diode circuit is configured to steer an electrostatic discharge current from an input/output pad to at least one of the first clamping circuit or the third power rail
Implementation Method 2
In order to prevent damages due to excessive voltage stress resulted from electrostatic discharge, ESD protection circuits are usually used to protect integrated circuits from electrostatic discharge
Data Source
AI summary
An electrostatic discharge (ESD) protection device includes a first clamping circuit, a second clamping circuit, and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is configured to steer an ESD current from an input/output pad to at least one of the first clamping circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.