ESD Clamping Circuit With Shunt Trigger for Hot-Plug Discrimination

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Solution Overview

Problem

Current ESD protection circuits in electronic devices often fail to effectively manage electrostatic discharge events, particularly in advanced manufacturing processes with lower voltage endurance, and may not adequately prevent damage to components during such events.

Innovation Solution

The proposed ESD protection circuit incorporates multiple ESD clamping circuits and a shunt circuit, utilizing transistors and bias circuits to create a discharge path between power lines during ESD events, ensuring reliable discharging capability while maintaining insulation during normal conditions, and includes an ESD detection circuit to differentiate between ESD and hot plug events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional ESD protection circuit is used, then ESD current can be bypassed during ESD events, but the circuit may not provide sufficient protection in advanced manufacturing processes with lower voltage endurance

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidApplicability to advanced manufacturing processes
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The ESD protection circuit is divided into multiple series-connected transistors (first transistor, second transistor, third transistor) between the first power line and second power line. This segmentation allows each transistor to withstand a portion of the total voltage, enabling the circuit to function in advanced manufacturing processes with lower voltage endurance per device component.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A shunt circuit is introduced as an intermediary component coupled to the control terminal of the first transistor. This shunt circuit includes a detection circuit that senses voltage conditions and activates the first transistor only when ESD events are detected, preventing false activation during normal hot plug operations while ensuring protection during actual ESD events.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the ESD protection circuit activates the discharge path during ESD events, then ESD current can be diverted, but the circuit may incorrectly activate during hot plug events causing unnecessary short-circuiting

Engineering Contradiction:
ImproveESD current diversionVSAvoidIncorrect short-circuiting during hot plug events
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The shunt circuit incorporates a detection circuit that provides feedback by monitoring voltage conditions at the control terminal of the first transistor. The detection circuit compares the detected voltage against reference voltages to determine whether an ESD event or hot plug event is occurring, enabling intelligent discrimination and appropriate response selection.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The circuit utilizes different voltage parameter thresholds to distinguish between ESD events and hot plug events. The detection circuit is configured to recognize the specific voltage characteristics of ESD events (typically higher voltage spikes) versus hot plug events (lower voltage changes), activating the protection path only when ESD-specific parameters are detected.

Inventive Principle:
Principle #35Parameter changes

3Strength

If multiple transistors are connected in series to reduce voltage stress on each component, then the circuit can withstand lower voltage per component, but the overall discharging capability may be reduced

Engineering Contradiction:
ImproveVoltage endurance of individual componentsVSAvoidESD current discharging capability
Core Design Contradiction:
StrengthVSPower

Solution Approach 1:

The circuit employs dynamic control mechanisms where the shunt circuit actively manages the activation state of the first transistor based on real-time detection of ESD events. During ESD events, the shunt circuit rapidly activates the first transistor to maximize current diversion capability, while during normal operation, the transistor remains inactive to prevent unnecessary power consumption and maintain circuit stability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The shunt circuit is pre-configured with detection circuitry that continuously monitors for ESD conditions before they fully develop. Upon detecting the onset of an ESD event, the shunt circuit preemptively activates the first transistor to establish the discharge path early in the ESD event sequence, maximizing the circuit's ability to divert current before it can damage protected components.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides robust ESD protection, ensuring reliable discharging capacity and preventing component damage, while being applicable to advanced manufacturing processes with lower voltage endurance and accurately distinguishing between ESD and hot plug events to avoid incorrect short-circuiting.

Implementation Method 1

The shunt circuit is configured to conduct the first terminal of the first transistor to the control terminal of the first transistor during a period of an ESD event to raise a voltage of the control terminal of the first transistor

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Data Source

PatentUS11824349B2Electrostatic discharge protection circuit
Publication Date: 2023.11.21 REALTEK SEMICON CORP
  • US11824349B2 patent drawing
  • US11824349B2 patent drawing
  • US11824349B2 patent drawing

AI summary

An electrostatic discharge (ESD) protection circuit is provided, which includes multiple ESD clamping circuits and a shunt circuit. The multiple clamping circuits comprise multiple transistors, respectively. The multiple transistors are coupled in series between a first power line and a second power line. A shunt circuit is coupled with a first terminal and a control terminal of a first transistor of the multiple transistors. The shunt circuit is configured to conduct the first terminal of the first transistor to the control terminal of the first transistor during a period of an ESD event to raise a voltage of the control terminal of the first transistor. The shunt circuit insulates the first terminal of the first transistor from the control terminal of the first transistor during a period outside the period of the ESD event.