ESD Protection Circuit with Dynamic Input Decoupling
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Solution Overview
Problem
Electrical circuits and devices are susceptible to damage from electrostatic discharge (ESD) events, and existing ESD protection circuits may not adequately protect against such events, particularly when the device is powered off.
Innovation Solution
The implementation of a switch circuit with a transmission gate and detection circuits that decouple input nodes during an ESD event, utilizing NMOS and PMOS transistors with bulk biasing circuits to prevent parasitic diode forward-biasing and manage voltage levels, thereby creating conductive paths to ground or positive power sources to dissipate ESD current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing ESD protection circuits are used, then ESD current can be dissipated during normal operation, but the device lacks adequate protection when powered off
Solution Approach 1:
The ESD protection circuit dynamically changes its configuration based on the power state. During normal operation, the circuit maintains standard ESD protection paths. When powered off, the circuit reconfigures to activate alternative protection mechanisms including parasitic diodes and leakage paths that were inactive during operation, ensuring continuous protection across all power states.
Solution Approach 2:
The invention introduces intermediate protection elements such as parasitic diodes and leakage paths that act as mediators between the input nodes and ground. These intermediaries provide additional current dissipation paths specifically activated when the device is powered off, bridging the protection gap that exists in conventional circuits during this state.
2Object-affected harmful factors
If switch circuit with transmission gate is used to decouple input nodes during ESD event, then ESD current path is blocked, but circuit complexity increases
Solution Approach 1:
The invention extracts the decoupling function from the main signal path by using transmission gates controlled by detection circuits. The transmission gates selectively disconnect input nodes from the internal circuitry only when ESD events are detected, separating the protection function from the normal signal transmission path and enabling conditional decoupling without permanently increasing complexity.
Solution Approach 2:
The detection circuits automatically detect ESD voltage conditions and autonomously control the transmission gates to decouple the input nodes. This self-service mechanism eliminates the need for external control logic or manual intervention, allowing the circuit to respond automatically to ESD threats while maintaining simplicity in the control architecture.
3Reliability
If NMOS and PMOS transistors with bulk biasing circuits are used, then parasitic diode forward-biasing is prevented, but device area increases
Solution Approach 1:
The bulk biasing circuits are applied selectively to specific transistor regions where parasitic diode forward-biasing is most likely to occur during ESD events. Rather than uniformly biasing all transistors in the circuit, the invention targets critical regions with bulk biasing, maintaining reliable parasitic diode control while minimizing the overall area overhead associated with bulk biasing infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively protects electrical components from ESD damage by decoupling input nodes and creating safe conductive paths, preventing stress on transistors and other components during ESD events, even when the device is powered off.
Implementation Method 1
a first-type transistor of a transmission gate coupled between the first signal node and the second signal node is turned off
Implementation Method 2
a first control node is electrically coupled with a first power node after the first power node is floating or electrically coupled to a second power node
Implementation Method 3
utilizing NMOS and PMOS transistors with bulk biasing circuits to prevent parasitic diode forward-biasing
Data Source
AI summary
A device includes a first power node, a second power node, a first input node, a second input node, a protected circuit, and a switch circuit. The protected circuit is coupled between the first power node and the second power node, and the protected circuit is further coupled with the second input node. The switch circuit is coupled with the first power node, the second power node, the first input node, and the second input node. The switch circuit is configured to electrically decouple the first input node and the second input node after (a) the first power node is floating or electrically coupled to the second power node and (b) a voltage level at the first input node is greater than a voltage level at the second power node by a predetermined voltage value.