ESD Detection Circuit with Dynamic Bias Control
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Solution Overview
Problem
Existing ESD protection circuits face issues with absorbing electrostatic signals of higher voltage amplitudes, leading to damage of gate-oxide layers and increased production costs, especially in advanced nano-scale CMOS processes, and require additional supply voltages for proper operation.
Innovation Solution
An ESD detection circuit comprising a triggering circuit, bias circuit, trigger controlling circuit, and activating control circuit, which generates an ESD trigger signal by controlling bias voltages and activating the ESD mode based on voltage levels, reducing voltage differences to manage trigger signal duration and prevent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ESD protection circuit uses a standard gate-oxide layer thickness, then the circuit can operate at normal supply voltages, but the gate-oxide layers will be damaged when voltage levels exceed normal supply voltage (e.g., 3*VDD)
Solution Approach 1:
The circuit is divided into multiple operational modes (normal mode and ESD mode) with distinct bias voltage configurations. The ESD detection circuit segments the voltage handling by routing high-voltage ESD signals through dedicated paths while maintaining standard gate-oxide protection for normal operation.
Solution Approach 2:
The bias voltages (first bias voltage and second bias voltage) are dynamically adjusted based on the detected voltage level at the first node. When ESD is detected, the trigger controlling circuit modifies the bias voltages to extend the discharge duration, adapting the circuit's response to the abnormal voltage condition.
2Reliability
If the ESD protection circuit uses a thicker gate-oxide layer process technique, then the gate-oxide layers can withstand higher voltage amplitudes, but the production cost increases
Solution Approach 1:
Instead of changing the physical gate-oxide layer thickness, the invention changes operational parameters (bias voltages) to achieve high-voltage withstand capability. The trigger controlling circuit adjusts bias voltages to extend discharge duration, allowing standard-thickness gate-oxide layers to handle ESD events without requiring expensive thicker-oxide processes.
3Reliability
If the ESD protection circuit uses triple well process, then the circuit can absorb electrostatic signals with greater voltage amplitudes, but the gate-driven technique becomes complicated and production cost increases
Solution Approach 1:
The ESD detection circuit is designed to work with standard CMOS processes while providing enhanced ESD protection. The circuit uses universal components (FETs, resistors, capacitors) configured to detect ESD events and trigger extended discharge, eliminating the need for specialized triple well processes or complex gate-driven techniques.
4Reliability
If the ESD protection circuit requires additional lower supply voltage, then the circuit can operate properly at high voltages, but the circuit requires more power supplies and becomes more complex
Solution Approach 1:
The circuit uses the existing supply voltage VDD and ground to generate the necessary bias voltages for ESD operation. The trigger controlling circuit derives the first and second bias voltages from the available power supplies, eliminating the need for additional lower supply voltages while maintaining proper circuit operation during ESD events.
Data Source
AI summary
An ESD detection circuit which includes: a triggering circuit for generating an ESD trigger signal when the ESD detection circuit is in ESD mode; a bias circuit for providing at least a first bias voltage and a second bias voltage for controlling the operation of the triggering circuit; a trigger controlling circuit for decreasing a voltage difference between the first bias voltage and the second bias voltage when the ESD detection circuit is in the ESD mode, and for controlling a duration of the ESD trigger signal that is generated by the triggering circuit; and an activating control circuit for activating the trigger controlling circuit and the triggering circuit to enter the ESD mode according to a voltage level at a first node.