High Voltage Tolerant ESD Device With Multiple Blocking Junctions
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Solution Overview
Problem
Designing high voltage tolerant ESD devices in SOI processes poses challenges due to cross-talk between devices, and existing solutions often require additional process steps, which is undesirable.
Innovation Solution
Implementing a high voltage tolerant ESD clamp using a snapback device with multiple blocking junctions and buried layers in a SOI process, such as an NPN BJT, BSCR, or zener diode, to reduce cross-talk and punch-through effects without adding extra process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple blocking junctions are formed in the drift region to increase voltage tolerance, then the voltage drop across anode and cathode increases, but the device complexity increases
Solution Approach 1:
The drift region is segmented into multiple sections by forming several blocking junctions (first, second, third blocking junctions) between the anode and cathode. Each blocking junction creates a separate depletion region that contributes to the cumulative voltage drop, thereby increasing the overall voltage tolerance of the device without requiring a single excessively deep junction.
Solution Approach 2:
The blocking junctions are formed by introducing n-type regions (n-wells or n-type implanted regions) at different lateral positions within the drift region. This lateral arrangement in the silicon plane, rather than simply increasing vertical depth, creates multiple blocking interfaces that collectively handle higher voltages while maintaining a manageable device structure.
2Object-affected harmful factors
If isolation regions are used between devices to reduce cross-talk, then cross-talk is reduced, but additional process steps are required
Solution Approach 1:
The isolation function is merged with the existing drift region structure. The drift region itself, which is necessary for the high-voltage blocking function, also serves as the isolation medium between adjacent ESD devices. By properly designing the drift region extensions and utilizing the natural depletion regions of the blocking junctions, electrical isolation is achieved without requiring separate isolation trenches or additional dielectric layers.
Solution Approach 2:
The drift region performs multiple functions simultaneously: it provides the necessary voltage blocking capability through its depleted state, creates the isolation barriers between adjacent devices through lateral extensions, and forms the basis for the multiple blocking junctions. This multi-functionality eliminates the need for dedicated isolation structures and additional processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves higher voltage tolerance across the anode and cathode terminals by cumulative voltage drops across multiple blocking junctions, effectively reducing cross-talk and punch-through while maintaining compatibility with existing process steps.
Implementation Method 1
the snapback device define a higher voltage drop across their anode and cathode due to the cumulative effect of the voltage drops across each blocking junction
Implementation Method 2
In order to reduce cross-talk between the blocking junctions, the snapback device is implemented in a SOI process
Implementation Method 3
in order to reduce punch-through effect the snapback device may include one or more buried layers, such as NBL or PBL, formed below the device
Data Source
AI summary
In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.