ESD Diode Layout With Buried Rails for Smaller Chip Area
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Solution Overview
Problem
When multiple diodes are arranged next to each other in an ESD protection circuit, the increased layout area leads to an expansion in the semiconductor device's chip size, which is undesirable.
Innovation Solution
The semiconductor device incorporates a substrate with impurity regions and interconnects arranged in a specific configuration to prevent the activation of parasitic bipolar transistors between neighboring diodes, thereby maintaining a smaller chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple diodes are placed next to each other in an ESD protection circuit, then the ESD protection functionality is improved, but the chip size increases
Solution Approach 1:
The patent introduces buried power rails extending in a direction perpendicular to the diode arrangement (second direction vs. first direction). This dimensional change allows power supply to multiple diodes without increasing the lateral spacing between them, enabling compact diagonal layouts that reduce chip area while maintaining ESD protection functionality
Solution Approach 2:
The patent merges the power supply function into the substrate structure itself by forming buried power rails within the substrate. Multiple diodes share common power and ground rails, eliminating the need for separate power supply interconnects for each diode and reducing overall layout area
2Reliability
If diodes are spaced apart to prevent parasitic bipolar transistor activation, then device reliability is improved, but the layout area increases
Solution Approach 1:
The patent introduces buried power rails as intermediary structures between adjacent diodes. These rails act as isolation barriers that prevent parasitic bipolar transistor activation while allowing diodes to be placed closer together, thus maintaining reliability without increasing layout area
Solution Approach 2:
The patent applies different conductivity types (first and second types) to different regions of the substrate to create localized electrical properties. By forming impurity regions with specific conductivity types in targeted locations, the patent prevents parasitic transistor formation locally while maintaining compact overall layout
Data Source
AI summary
A first impurity region and a second impurity region, having first and second types of conductivity, respectively, are formed on a substrate, spaced apart from each other in a first direction, in contact with a third impurity region a fourth impurity region, which are also provided on the substrate with the second and first types of conductivity, respectively. Interconnects that extend in a second direction, which is different from the first direction, are formed in the substrate, on the side of the third impurity region facing the fourth impurity region side, and on the side of the fourth impurity region facing the third impurity region. By this means, when multiple diodes are arranged next to each other, it is still possible to prevent or substantially prevent the semiconductor device's chip size from increasing.