Low Capacitance ESD Diodes via Modified Doping
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Solution Overview
Problem
Integrated circuits face challenges with existing ESD protection diodes due to high capacitance, which limits their operating frequency and introduces voltage overshoot during electrostatic discharge events, particularly from human body, machine, and charged device models.
Innovation Solution
The development of shallow trench isolated and gate space isolated ESD protection diodes with reduced capacitance is achieved by modifying the doping concentrations and structures, such as removing the pwell under the N+ diffusion and forming counter doped nwells, which increases the depletion region width and reduces diode capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection diodes are used, then ESD current can be handled, but high capacitance limits operating frequency and causes voltage overshoot
Solution Approach 1:
The patent modifies the doping concentrations in the diode structure, specifically using lighter doping in the substrate and well regions compared to conventional designs. This parameter change increases the depletion region width, which directly reduces the junction capacitance of the ESD diode, thereby enabling higher operating frequencies while maintaining ESD protection
Solution Approach 2:
The patent introduces a vertical depletion region extension by modifying the doping profile in the depth dimension. By creating a lightly doped region that extends vertically beneath the junction, the depletion region is expanded in the vertical dimension, reducing capacitance without increasing lateral footprint
2Reliability
If conventional ESD protection diodes are used, then ESD current can be shunted, but voltage overshoot occurs during fast rise time ESD events
Solution Approach 1:
By changing the doping parameters to create a more gradual doping gradient and lighter overall doping levels, the depletion region width increases. This reduces the junction capacitance, allowing the diode to respond faster to ESD transients and reduce voltage overshoot during fast rise time events
3Productivity
If diode capacitance is reduced by increasing depletion region width, then operating frequency increases, but ESD current handling capability may be compromised
Solution Approach 1:
The patent applies different doping concentrations to different regions: lighter doping in the substrate and well regions to reduce capacitance, while maintaining heavier doping in the contact regions to ensure low series resistance. This local quality differentiation allows the diode to simultaneously achieve high frequency operation and strong ESD current handling capability
Solution Approach 2:
The diode structure employs a composite doping profile with multiple regions of different doping concentrations. This composite structure creates an optimized balance between depletion region width (for low capacitance) and conductive regions (for low resistance), enabling both high frequency operation and robust ESD protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces diode capacitance, preventing voltage overshoot and enabling integrated circuits to operate at higher frequencies while maintaining effective ESD current handling capabilities.
Implementation Method 1
removing the pwell under the N+ diffusion and forming counter doped nwells, which increases the depletion region width and reduces diode capacitance
Data Source
AI summary
An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.