ESD Diode Insulating Pads Reduce Dielectric Thickness
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Solution Overview
Problem
Conventional semiconductor manufacturing processes require a thicker dielectric layer for electrostatic discharge (ESD) protection, which increases the area and instability, especially in smaller linewidth designs, due to the need for advanced chemical mechanical polishing (CMP) processes.
Innovation Solution
A semiconductor device with an ESD protection structure featuring a diode between the gate and source, utilizing insulating pads and a thinner dielectric layer, where the insulating pads serve as etch stops, allowing for reduced dielectric thickness and simplified CMP processes, thereby minimizing waste and processing difficulties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker dielectric layer is deposited to ensure process margin for CMP, then the process stability is improved, but the area increases and tube core performance is sacrificed
Solution Approach 1:
The patent applies different dielectric layer thicknesses to different regions of the device. Specifically, the first dielectric layer has a first thickness in a first region and a second thickness in a second region, where the thickness varies locally to match the specific process requirements of each area. This resolves the contradiction by providing sufficient thickness where needed for CMP stability while minimizing area occupation in other regions.
2Reliability
If a thicker dielectric layer is used for ESD protection, then the ESD protection capability is improved, but the manufacturing complexity and cost increase due to advanced CMP requirements
Solution Approach 1:
The patent implements local quality by depositing dielectric layers with different thicknesses in different regions. The first dielectric layer has varying thickness (first thickness in first region, second thickness in second region) that provides adequate ESD protection capability where required while avoiding the need for uniformly thick dielectric layers across the entire device, thereby reducing manufacturing complexity and CMP process requirements.
3Manufacturing precision
If a uniform thick dielectric layer is deposited throughout the device, then the process margin is ensured, but the productivity decreases due to increased deposition time and difficulty in etching contact holes
Solution Approach 1:
The patent applies local quality by depositing dielectric layers with spatially varying thicknesses. The first dielectric layer has a first thickness in a first region and a second thickness in a second region, ensuring adequate process margin in critical areas while reducing deposition time and etching difficulty in non-critical areas, thereby improving overall manufacturing efficiency without sacrificing necessary process margins.
Data Source
AI summary
A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.