ESD Protection Diode Structure With Lateral Bipolar Turn-On

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Solution Overview

Problem

Conventional ESD protection diodes face issues with responsiveness and load capacitance, leading to potential gate oxide film breakdown and poor discharge performance, particularly in low and high withstand voltage scenarios.

Innovation Solution

Incorporation of a lateral bipolar transistor into the ESD protection diode structure, comprising two pairs of PN diodes and a diffusion layer with a different polarity connected to the cathode or anode electrode, enhancing the diode's responsiveness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional gate diode structure is used to reduce junction capacitance, then the diode achieves fast turn-on time and high conductance, but the existing process flow must be changed and load capacitance problems arise

Engineering Contradiction:
Improveturn-on timeVSAvoidprocess flow change
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The patent merges the ESD protection diode with the existing gate diode structure, combining the protective function with the existing circuit element. The ESD diode shares the gate electrode and insulating layer with the gate diode, integrating multiple functions into a unified structure that eliminates the need for separate process flows while achieving both fast turn-on and reduced capacitance

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate diode structure is designed to serve dual purposes: its primary function as a gate control element and its secondary function as an ESD protection device. By making the gate diode universally functional, the patent eliminates the need for additional dedicated ESD protection structures and process changes, thereby maintaining fast turn-on characteristics while avoiding manufacturing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the well concentration is reduced to secure withstand voltage in high withstand voltage diodes, then the gate oxide film thickness can be increased, but the resistance component increases and responsiveness deteriorates

Engineering Contradiction:
Improvewithstand voltageVSAvoidresponsiveness
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies local quality by creating different doping concentrations in specific regions of the semiconductor substrate. The well region has a first concentration optimized for withstand voltage, while the drift region has a second concentration optimized for responsiveness. This spatial variation in doping quality allows each region to perform its specific function optimally without compromising the other

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The semiconductor structure is segmented into distinct functional regions with different doping characteristics. The well region and drift region are separated and independently optimized, allowing the well to provide high withstand voltage capability while the drift region maintains low resistance for fast responsiveness. This segmentation resolves the contradiction by distributing different functional requirements to different spatial zones

Inventive Principle:
Principle #1Segmentation

3Reliability

If an ESD protection diode is used for low withstand voltage applications, then the gate oxide film is thin, but overshoot voltage causes gate oxide film breakdown

Engineering Contradiction:
Improveprotection capabilityVSAvoidgate oxide film breakdown
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements beforehand cushioning by designing the drift region with optimized doping concentration and thickness to cushion and absorb the overshoot voltage before it reaches the gate oxide film. The drift region acts as a voltage buffer that prevents harmful voltage spikes from directly stressing the thin gate oxide, thereby protecting against breakdown while maintaining low withstand voltage operation

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed structure improves the ESD protection diode's responsiveness, reducing overshoot voltage and increasing CDM withstand voltage by leveraging the parasitic bipolar transistor's high current amplification factor.

Implementation Method 1

Incorporation of a lateral bipolar transistor into the ESD protection diode structure, comprising two pairs of PN diodes and a diffusion layer with a different polarity connected to the cathode or anode electrode, enhancing the diode's responsiveness

Methodology Applied
Scientific EffectParasitic bipolar transistor effect:

Data Source

PatentEP4632817A1ESD protection diode and structure thereof
Publication Date: 2025.10.15 NISSHINBO MICRO DEVICES INC
  • EP4632817A1 patent drawingFigure 1~2
  • EP4632817A1 patent drawingFigure 3~4
  • EP4632817A1 patent drawingFigure 5~6

AI summary

An ESD protection diode includes two pairs of PN diodes in a semiconductor substrate (10), the two pairs of PN diodes being respectively formed of P-type and N-type diffusion layers (23, 24; 31, 32). The ESD protection diode includes a lateral bipolar transistor disposed between the two pairs of PN diodes in the semiconductor substrate, and the lateral transistor includes an P-type diffusion layer (25) having a polarity different from that of each terminal connected to an anode electrode (1), and the P-type and N-type diffusion layers (23, 24; 31, 32) The lateral bipolar transistor includes the first and second P-type diffusion layers (23, 24) connected to the anode electrode (1), the third P-type diffusion layers (25) formed between the first and second P-type diffusion layers (23, 24) and connected to a cathode electrode (2), and the first and second N-type diffusion layers (31, 32) formed in an N-type well (11) in the semiconductor substrate (10).