Segmented ESD Diode Structure for LCD Substrate Area Optimization
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Solution Overview
Problem
Conventional ESD protection devices for LCD panels have limited electrostatic discharge protection ability and occupy significant substrate area, and their functionality is compromised if the gate is damaged, reducing reliability and layout efficiency.
Innovation Solution
A diode structure with a semiconductor pattern, first and second conductor patterns, and an insulating layer, where the top conductor pattern is electrically connected to both, allowing for enhanced static electricity conduction and maintaining functionality even if the bottom or top conductor pattern is damaged, with the option to form multiple diodes connected in parallel for improved protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection devices are formed on the substrate, then electrostatic discharge protection is provided, but the substrate area available for layout is reduced
Solution Approach 1:
The gate electrode is divided into multiple independent gate electrodes (first gate electrode, second gate electrode, etc.), each capable of functioning as an independent ESD protection device. This segmentation allows the ESD protection function to be distributed across multiple smaller units, reducing the area occupied by each individual protection device while maintaining overall protection capability.
Solution Approach 2:
The gate insulating layer serves multiple functions: it acts as the insulating layer for the gate electrode, serves as the tunnel insulating layer for ESD protection, and functions as part of the pixel electrode structure. This multi-functionality eliminates the need for separate dedicated ESD protection structures, thereby reducing substrate area consumption.
2Reliability
If multiple ESD protection devices are fabricated to enhance protection ability, then ESD protection capability is improved, but the substrate area occupied increases
Solution Approach 1:
Multiple ESD protection functions are merged into a single integrated structure where the gate insulating layer provides tunneling protection for multiple gate electrodes simultaneously. The pixel electrode structure is combined with the ESD protection structure, allowing multiple protection devices to share common components and reduce total area occupation.
3Device complexity
If the gate in the ESD protection device is damaged or disconnected, then the device stops operating, but this reduces reliability
Solution Approach 1:
The gate electrode is segmented into multiple independent gate electrodes, each with its own gate insulating layer providing ESD protection. If one gate electrode or its gate insulating layer is damaged, the other segmented units continue to function independently, maintaining overall system reliability through functional redundancy.
Solution Approach 2:
The gate insulating layer is designed to function as a tunnel insulating layer that can absorb and dissipate electrostatic discharge energy before it reaches the channel layer. This beforehand cushioning protects the critical channel structure from damage, preventing complete device failure even under ESD stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed ESD protection circuit achieves better electrostatic discharge protection with fewer diodes, increasing available substrate area and ensuring partial functionality even if one conductor pattern is damaged, thus enhancing reliability and layout flexibility.
Implementation Method 1
When the electrostatic discharge phenomenon occurs, the foregoing ESD protection device 100 can consume the electrostatic energy and lead the static electricity out, so as to prevent the devices in the LCD panel from being damaged by electrostatic discharge.
Data Source
AI summary
A diode disposed on a substrate is provided. The diode includes a semiconductor pattern, a first conductor pattern, a second conductor pattern, an insulating layer, and a top conductor pattern. The first conductor pattern and the second conductor pattern are respectively disposed on a portion of the semiconductor pattern. The insulating layer is disposed on the first conductor layer, the second conductor layer, and the semiconductor pattern. Moreover, the top conductor pattern is disposed on the insulating layer above the semiconductor pattern and electrically connected to the first conductor pattern. In the diode mentioned above, no circuit belonging to the diode is disposed under the semiconductor pattern. Therefore, when the aforementioned diode and other devices are integrated, layout of the devices can adopt the space under the diode.