Substrate-Less ESD Diode Pedestal Structure for Higher Current

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The challenge in fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures is the reduction in current carrying capacity due to the thinning of the silicon substrate, which leads to increased reverse bias diode leakage and stability concerns with fin height, particularly in lateral diode architectures.

Innovation Solution

The implementation of fin profile engineering to create a semiconductor pedestal at the base of Si fins, using selective implantation or integration of different materials, which slows down the etch rate in ESD diode regions, thereby increasing current carrying capacity without requiring taller fin heights.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the silicon substrate is thinned in substrate-less technology, then device integration density is improved, but current carrying capacity of ESD diodes deteriorates

Engineering Contradiction:

Improvedevice integration densityVSAvoidcurrent carrying capacity

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by creating a semiconductor pedestal structure specifically at the base of Si fins in ESD diode regions, while other areas maintain the thinned substrate architecture. This localized structural modification concentrates the current carrying function at the pedestal base without affecting the overall thin-substrate high-density integration benefit.

Inventive Principle:

Principle #3Local quality

2Reliability

If fin height is increased to improve current carrying capacity, then ESD diode performance is improved, but fin stability deteriorates

Engineering Contradiction:

ImproveESD diode performanceVSAvoidfin stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent transitions from a one-dimensional fin structure to a three-dimensional pedestal-based structure. By adding vertical extent at the base and creating a broader footprint, the current carrying path is extended in multiple dimensions without requiring proportional increases in fin height, thus maintaining fin stability while improving ESD performance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If lateral diode architecture is used to reduce area, then device density is improved, but reverse bias leakage increases

Engineering Contradiction:

Improvedevice areaVSAvoidreverse bias leakage

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The semiconductor pedestal acts as an intermediary structure between the thinned substrate and the ESD diode junction. It provides a controlled transition region that manages the reverse bias characteristics, reducing leakage currents while maintaining the compact lateral diode architecture benefits.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12166031B2Substrate-less electrostatic discharge (ESD) integrated circuit structures

Publication Date: 2024.12.10 INTEL CORP

AI summary

Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.