ESD Diode for RF Noise Optimization
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Solution Overview
Problem
Conventional ESD protection schemes for internal logic circuits in RF front-end circuits, such as low-noise amplifiers, degrade RF circuit performance due to induced parasitic capacitance, which negatively impacts noise figure and impedance matching.
Innovation Solution
A secondary ESD protection circuit using a single diode coupled between the gate and source terminals of an NMOS transistor, providing both ESD protection and noise optimization by acting as a capacitor during normal operation and a discharge path during ESD events, replaces the conventional gate-grounded NMOS transistor and noise reducing capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits (GGNMOS device) are used for CDM protection, then ESD protection is provided, but parasitic capacitance increases which degrades RF circuit performance
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect by replacing the conventional GGNMOS device with a diode-based protection circuit. The diode configuration removes the large parasitic capacitance source while maintaining ESD protection functionality, directly addressing the contradiction between protection reliability and harmful parasitic effects.
Solution Approach 2:
The patent changes the key parameter of capacitance by substituting the GGNMOS device with a diode structure that has significantly lower parasitic capacitance. This parameter change allows the circuit to maintain ESD protection while reducing the harmful capacitance that degrades RF performance, particularly noise figure and impedance matching.
2Reliability
If GGNMOS device is added for secondary ESD protection, then CDM protection is achieved, but noise figure deteriorates
Solution Approach 1:
The patent removes the GGNMOS device that generates excessive parasitic capacitance and replaces it with a diode-based circuit. This extraction eliminates the source of noise figure deterioration while preserving the essential CDM protection function through the diode's voltage-clamping behavior during ESD events.
Solution Approach 2:
The patent uses a simple diode structure instead of the complex GGNMOS device. The diode provides the necessary protection function with minimal parasitic effects, effectively replacing the more complex component that caused noise figure issues with a simpler, more suitable component for RF applications.
3Reliability
If GGNMOS device is placed near RF input pins, then ESD protection coverage is improved, but impedance matching is significantly impacted
Solution Approach 1:
The patent extracts the impedance-matching-degrading element (GGNMOS device) and replaces it with a diode-based protection circuit. The diode provides comparable ESD protection coverage when placed near the RF input pins without significantly affecting the impedance matching, as it introduces minimal parasitic capacitance compared to the GGNMOS structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces parasitic capacitance effects, improving RF performance by reducing noise figure and maintaining impedance matching, as demonstrated by simulation results showing a 70% reduction in noise figure from 10.3 dB to 3.24 dB at 5.8 GHz.
Implementation Method 1
A secondary ESD protection circuit is coupled between the RF input and the second power supply node. The secondary ESD protection circuit includes a secondary ESD protection diode coupled between the gate and source terminals of the NMOS transistor.
Data Source
AI summary
A RF device includes a RF integrated circuit having a RF input and a RF output. The RF integrated circuit has an NMOS transistor having a gate terminal coupled to the RF input, a drain terminal coupled to a first power supply node and a source terminal coupled to a second power supply node. The RF integrated circuit is vulnerable to damage from an ESD event. A primary ESD protection circuit is coupled to the RF input and between the first and second power supply nodes. A secondary ESD protection circuit is coupled between the RF input and the second power supply node. The secondary ESD protection circuit includes a secondary ESD protection diode coupled between the gate and source terminals of the NMOS transistor.