ESD Protection Circuit With Feedback Delay for Complete Discharge
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Solution Overview
Problem
Existing electrostatic discharge (ESD) protection circuits fail to completely discharge electrostatic charges due to a discharge transistor on period that is not long enough, leading to incomplete protection and potential damage to integrated circuit functional circuits.
Innovation Solution
An ESD protection circuit incorporating a pulse detection unit, a discharge transistor, a feedback delay unit, and a processing unit, where the feedback delay unit extends the on period of the discharge transistor using PMOS and NMOS transistors to ensure thorough discharge without increasing layout size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the discharge transistor on period is extended to ensure complete discharge, then the electrostatic protection effect is improved, but the layout area increases
Solution Approach 1:
The feedback delay unit is nested within the existing ESD protection circuit structure, with PMOS and NMOS transistors integrated into the discharge path. This allows the discharge transistor to maintain an extended on-period through feedback control without requiring additional external components or increasing the overall layout area, as the delay mechanism is embedded within the existing transistor architecture.
Solution Approach 2:
The discharge transistor's on-period is made dynamic through the feedback delay unit, which extends the conduction time based on the detected electrostatic charge levels. The PMOS and NMOS transistors work in conjunction to provide time-delayed feedback control, allowing the discharge transistor to remain active longer when needed while automatically adjusting its operation without requiring a larger physical footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures complete discharge of electrostatic charges, reducing the risk of damage to integrated circuit functional circuits while minimizing layout space occupation and avoiding false triggering.
Implementation Method 1
The discharge transistor is configured to enable a conduction between the source and the drain to discharge electrostatic charges
Implementation Method 2
The feedback delay unit includes a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor
Data Source
AI summary
Embodiments provide an electrostatic discharge (ESD) protection circuit and an electrostatic discharge method. The ESD protection circuit includes: a pulse detection unit (100), a discharge transistor (300), a feedback delay unit (200), and a processing unit (400). A first terminal of the pulse detection unit (100) is connected to a first pad (101), a second terminal of the pulse detection unit (100) is connected to a second pad (102), and an output terminal of the pulse detection unit (100) is configured to output a detection result signal. A gate of the discharge transistor (300) is connected to the output terminal of the pulse detection unit (100), a drain of the discharge transistor (300) is connected to the first pad (101), and a source of the discharge transistor (300) is connected to the second pad (102). The feedback delay unit (200) includes a PMOS transistor (Mp) and an NMOS transistor (Mn).