ESD Protection Circuit with Gated Diode Biasing
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Solution Overview
Problem
Semiconductor component manufacturers face challenges in designing ESD protection structures that are both effective and cost-efficient, as large structures required for maximal ESD protection increase capacitance, leading to slow device performance in high-frequency applications.
Innovation Solution
A capacitance modulation circuit using gated diodes with a biasing circuit that depletes charge carriers from the channel region to create depletion capacitance, reducing the overall capacitance of the ESD protection network and allowing for larger ESD protection structures without impacting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ESD protection structures are made large to provide maximal ESD protection, then the ESD protection capability is improved, but the capacitance associated with the input and output pads increases, making the devices unacceptably slow
Solution Approach 1:
The patent applies dynamics by making the ESD protection structure's capacitance adjustable rather than fixed. A control circuit dynamically changes the capacitance value based on operational requirements, allowing the structure to provide strong ESD protection when needed while maintaining low capacitance for high-speed operation during normal conditions.
Solution Approach 2:
The patent changes the capacitance parameter of the ESD protection structure by introducing a control circuit that can modify the capacitance value. This allows the system to switch between different capacitance states - a first capacitance value for high-speed operation and a second, higher capacitance value for enhanced ESD protection.
2Reliability
If the ESD protection structures are made large to provide maximal ESD protection, then the ESD protection capability is improved, but the semiconductor area occupied by the ESD protection circuit increases, increasing manufacturing costs
Solution Approach 1:
The patent uses dynamics to make the protection capability adjustable. Instead of always using a large ESD protection structure that occupies significant area, the system dynamically activates enhanced protection only when needed, allowing for a more area-efficient design that provides adequate protection without permanently allocating excessive semiconductor real estate.
Solution Approach 2:
The patent changes the operational parameters of the ESD protection circuit to allow a single structure to provide varying levels of protection. By modifying the capacitance parameter through the control circuit, the same physical structure can deliver different protection capabilities, eliminating the need for multiple structures of different sizes and reducing total area requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher frequency performance and cost-efficient ESD protection by reducing capacitance during normal operation, allowing I/O pads to handle higher frequency signals while preventing damage to the gated diodes during ESD events.
Implementation Method 1
depleting charge carriers from the at least one channel region to form a depletion capacitance in the at least one channel region that is in series with a diode junction capacitance
Data Source
AI summary
An electrostatic discharge (ESD) protection circuit and a method for reducing capacitance in the ESD protection circuit. A pair of gated diodes are connected in series, wherein the anode of one of the gated diodes is coupled to a lower voltage supply node and the cathode the other gated diode is connected to the upper voltage supply node. The commonly connected anode and cathode of the series connected gated diodes are connected to an input/output pad and to receiver and driver circuitry. The gates of the gated diodes are connected together. A gate biasing circuit is connected to the gates of the gated diodes. The gate biasing circuit applies a voltage to the gates of the gated diodes and depletes their channel regions of charge carriers, which lowers the capacitances of each gate diode.