ESD Protection Circuit With Higher Holding Voltage Against Latch-Up
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Solution Overview
Problem
Semiconductor integrated circuit devices face issues with latch-up and undesired ESD protection device operation due to holding voltage being lower than operational voltage, leading to continuous current bypass and reduced ESD stress tolerance.
Innovation Solution
The ESD protection device incorporates a P type diode region, boundary regions, and a GGNMOS transistor structure with a silicide layer, where the diode region is connected to a pad with a bias, and the boundary regions increase the holding voltage by controlling resistance, preventing latch-up and enhancing ESD current tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the holding voltage is increased to prevent latch-up, then the reliability is improved, but the trigger voltage also increases so that the ESD protection device cannot be rapidly driven when static electricity is generated
Solution Approach 1:
The patent modifies the electrical parameters of the ESD protection device by introducing a body bias voltage to the substrate. This changes the holding voltage and trigger voltage characteristics dynamically, allowing the device to maintain high reliability while preserving rapid trigger response. The body bias voltage adjusts the potential distribution in the semiconductor substrate, effectively decoupling the holding voltage from the trigger voltage increase.
2Device complexity
If the holding voltage is lower than the operational voltage, then the device complexity is reduced, but ESD stresses are generated during operation resulting in undesired timing and continuous current bypass
Solution Approach 1:
The patent implements a feedback mechanism where the body bias voltage is applied to the substrate based on the operational state of the ESD protection device. This feedback control adjusts the holding voltage to be higher than the operational voltage only when needed, preventing latch-up and undesired ESD stresses while maintaining simple device structure during normal operation.
3Productivity
If the ESD protection device continuously bypasses current due to holding voltage being lower than operational voltage, then the productivity is improved through current bypass capability, but latch-up occurs between power voltage terminal and ground terminal
Solution Approach 1:
The patent applies a counteracting body bias voltage to the substrate that opposes and balances the voltage differential between the operational voltage and holding voltage. This counterweight effect prevents the continuous current bypass that would otherwise cause latch-up, while still allowing the ESD protection device to maintain its current bypass capability for ESD protection when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the holding voltage, reducing latch-up occurrences and improving ESD current tolerance, allowing for rapid response to static electricity and efficient ESD current discharge.
Implementation Method 1
the boundary regions increase the holding voltage by controlling resistance
Implementation Method 2
an electrostatic discharge (ESD) protection device for protecting an internal circuit
Data Source
AI summary
An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.