ESD Protection Circuit With JFET Clamp for Residual Charge
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Solution Overview
Problem
Snapback devices used for electrostatic discharge (ESD) protection in integrated circuits often fail to completely dissipate ESD charges, leading to over-voltage conditions that can damage sensitive devices on the integrated circuit.
Innovation Solution
An additional transistor, specifically a p-type junction field-effect transistor (JFET), is introduced between the protected node and ground. This transistor is biased such that it remains off until the voltage on the protected node exceeds a certain threshold, at which point it turns on, ensuring continued discharge of any remaining ESD charge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a snapback device is used for ESD protection, then most of the ESD charge is dissipated, but enough charge remains on the I/O pad to cause over-voltage that can damage sensitive devices
Solution Approach 1:
A second transistor is introduced as an intermediary component between the protected node and ground. This transistor activates when the first transistor shuts off and provides an additional discharge path for remaining ESD charge, ensuring complete energy dissipation and preventing over-voltage damage to sensitive devices.
2Power
If the parasitic bipolar transistor remains on to dissipate ESD charge, then ESD is dissipated to ground, but when current falls below holding current the transistor shuts off leaving residual charge
Solution Approach 1:
The second transistor is designed to activate automatically when the first transistor shuts off due to falling current. This ensures continuous charge dissipation action without interruption, maintaining the protective function throughout the entire ESD event duration until all excess charge is safely discharged.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The additional transistor ensures that the voltage on the protected node is maintained below a safe threshold, preventing damage to sensitive devices on the integrated circuit even after the primary snapback device has turned off.
Implementation Method 1
The very high voltage causes an avalanche breakdown at the junction between the source and the channel region of the MOSFET. The breakdown injects current into the channel region, which is the base of parasitic transistor.
Implementation Method 2
An additional transistor, specifically a p-type junction field-effect transistor (JFET), is introduced between the protected node and ground. This transistor is biased such that it remains off until the voltage on the protected node exceeds a certain threshold, at which point it turns on, ensuring continued discharge of any remaining ESD charge.
Data Source
AI summary
Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.