ESD Device Trigger Voltage Reduction via LDD Structure
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Solution Overview
Problem
Conventional ESD devices in high voltage processes have large areas and poor ESD performance due to deep N-type and P-type wells, making it difficult to trigger at moderate voltages, leading to inadequate protection against electrostatic discharge events in integrated circuits.
Innovation Solution
The implementation of a high voltage LDD structure in ESD devices with a semiconductor substrate, featuring a first and second lightly-doped-drain region and an emitter region, which reduces the trigger voltage and enhances protection by optimizing the depth and doping concentration of these regions to achieve lower trigger voltages for bipolar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deep N-type and P-type wells are used in high voltage ESD devices, then the device can handle high voltage, but the trigger voltage becomes too high and the device area becomes large
Solution Approach 1:
The patent applies local quality by creating a lightly-doped drain (LDD) region with specific doping concentration and depth parameters that differ from both the deep well and the surface region. This localized structural modification with graded doping enables the ESD device to trigger at lower voltages while maintaining high voltage handling capability, thereby reducing the required device area without compromising protection reliability
Solution Approach 2:
The patent changes the doping parameters (concentration and depth) of the drain region by introducing a lightly-doped drain structure. By adjusting the doping concentration to be lower than the deep well but higher than the channel, and controlling the depth to be shallower than the deep well, the patent achieves lower trigger voltage and reduced device area while maintaining ESD protection capability
2Reliability
If conventional deep N-type and P-type wells are used in high voltage ESD devices, then the device can handle high voltage, but the trigger voltage becomes too high
Solution Approach 1:
The patent introduces a lightly-doped drain region with intermediate doping concentration between the deep well and the channel, creating a graded doping profile. This local structural modification reduces the electric field concentration at the drain junction, enabling the bipolar transistor to trigger at lower voltages (reducing the harmful high trigger voltage) while maintaining the deep well's high voltage blocking capability
Solution Approach 2:
The lightly-doped drain region acts as an intermediary structure between the deep well and the channel. It provides a transition zone with intermediate doping characteristics that facilitates lower voltage triggering by reducing junction breakdown voltage, while the deep well below maintains the high voltage handling capability, thus mediating between the conflicting requirements
3Device complexity
If conventional simple N+/P-well or P+/N-well diodes are used, then the device structure is simple, but the ESD performance is poor and area is large
Solution Approach 1:
The patent merges the MOSFET structure with a bipolar ESD protection mechanism by integrating a lightly-doped drain region that enables bipolar transistor action. This combination allows the device to function as both a high voltage switch and an ESD protection device with low trigger voltage, achieving good ESD performance without requiring a completely separate protection structure, thus maintaining reasonable device complexity
Data Source
AI summary
A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.