ESD Circuit Leakage Compensation via Replica Transistor
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Solution Overview
Problem
ESD protection circuits often experience latch-on conditions due to leakage current through trigger transistors after an ESD event, especially at high temperatures or in smaller process nodes, which can prevent the hold node from returning to a non-trigger voltage, leading to circuit malfunction.
Innovation Solution
Incorporating a replica trigger transistor with similar leakage characteristics to the main trigger transistor, which generates compensation current to the hold node, matching or slightly exceeding the leakage current, to prevent latch-on by ensuring the hold node returns to its non-trigger state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the trigger transistor leakage current is increased to improve detection sensitivity, then ESD event detection capability is enhanced, but the latch-on condition risk increases due to higher leakage current
Solution Approach 1:
The feedback mechanism using the replica trigger transistor dynamically measures the leakage current and adjusts compensation current accordingly. This allows the system to maintain high detection sensitivity while automatically compensating for the harmful leakage effects, preventing latch-on conditions even when detection sensitivity is enhanced.
Solution Approach 2:
The patent converts the harmful leakage current into a useful signal by using the replica transistor to sense and measure the leakage current. This measured leakage current then controls the compensation current source, transforming the previously harmful effect into a beneficial feedback signal that prevents latch-on and improves circuit reliability.
Data Source
AI summary
An ESD protection circuit includes a trigger transistor that is responsive to a detection signal indicating an ESD event. The trigger transistor pulls the voltage of a hold node towards a voltage of a power supply rail in response to the detection signal indicating an ESD event. The ESD protection circuit includes a replica trigger transistor whose leakage current controls current provided to the hold node after the detection signal no longer indicates an ESD event to compensate for leakage current through the trigger transistor.