ESD Protection Circuit Using Segmented N-Transistors
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Solution Overview
Problem
Existing ESD protection circuits require a larger circuit area to achieve effective current diversion, particularly due to the need for P-type transistors to handle both positive and negative voltages, which is inefficient in terms of space and functionality.
Innovation Solution
The ESD protection circuit incorporates a first and second N-type transistor with a deep N-well and P-well structure, along with diodes, to provide an efficient current diverting path for both positive and negative ESD voltages, reducing the overall circuit area by utilizing N-type transistors with better electron mobility and forming bipolar transistors as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a P-type transistor is used to handle both positive and negative voltages in an ESD protection circuit, then the circuit can provide comprehensive voltage protection, but the circuit area increases significantly
Solution Approach 1:
The ESD protection circuit is segmented into two separate N-type transistors: a first N-type transistor for handling positive voltage ESD events and a second N-type transistor for handling negative voltage ESD events. This segmentation allows each transistor to be optimized for its specific voltage polarity, reducing the overall circuit area compared to using a single P-type transistor that must handle both polarities
Solution Approach 2:
The invention changes the fundamental parameter of transistor type from P-type to N-type, and further optimizes by introducing deep N-well structures. This parameter change enables better electron mobility and smaller device footprint while maintaining comprehensive voltage protection capability through the dual-transistor configuration
2Reliability
If the P-type transistor size is increased to improve current diverting effect, then the ESD protection capability is enhanced, but the circuit area occupied increases
Solution Approach 1:
The invention changes the transistor type parameter from P-type to N-type, which has superior electron mobility characteristics. This parameter change allows for achieving the same or better ESD protection capability with a smaller device area, as N-type transistors can handle the same current density in a smaller footprint compared to P-type transistors
Solution Approach 2:
The invention employs deep N-well structures nested within the N-type transistors, creating a multi-layered semiconductor structure. This nesting approach allows for optimized current paths and enhanced ESD protection capability within a compact area, as the deep N-well provides additional current diversion paths without significantly increasing the lateral device footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for effective ESD protection with a smaller circuit area, enhancing the ability to divert currents during ESD events while maintaining performance across both positive and negative voltage conditions.
Implementation Method 1
The ESD protection circuit incorporates a first and second N-type transistor with a deep N-well and P-well structure, along with diodes, to provide an efficient current diverting path for both positive and negative ESD voltages, reducing the overall circuit area by utilizing N-type transistors with better electron mobility
Data Source
AI summary
The present application belongs to field of integrated circuit and discloses an electrostatic discharge protection circuit comprising a first N-type transistor and a second N-type transistor. The first N-type transistor comprises a first gate terminal coupled to a ground terminal; a first electrode terminal coupled to the first gate terminal; and a second electrode terminal. The second N-type transistor comprises a second gate terminal coupled to a metal pad; a third electrode terminal coupled to the second gate terminal; a fourth electrode terminal, coupled to the second electrode terminal; and a first deep N well, disposed under the third electrode terminal and the fourth electrode terminal. The ESD protection circuits provided by the embodiments of the present application have advantages of small circuit area and good ESD protection.