ESD Network Via-Connected Inductive Shunt
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Solution Overview
Problem
Current electrostatic discharge (ESD) devices are large and inefficiently use valuable chip space, often failing due to thin underpass connections, especially in small nodes like 90 nm and below, and are prone to damage from ESD events in semiconductor devices.
Innovation Solution
An ESD network connected in series to a through wafer via structure, which includes an inductive coil under the bond pad, providing a low resistance path to ground and eliminating the need for additional silicon elements, thus preserving chip space and enhancing robustness by reducing substrate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ESD devices are used to protect semiconductor devices, then ESD protection is provided, but valuable chip space is consumed and the devices are prone to failure due to thin underpass connections
Solution Approach 1:
The ESD protection circuit is merged with the bond pad structure by placing the ESD circuit directly under the bond pad. This integration allows the ESD protection function to be provided without consuming additional chip space, as the ESD circuit shares the space already allocated for the bond pad structure.
Solution Approach 2:
The invention transitions from a planar ESD device layout to a vertical three-dimensional structure. The ESD circuit is positioned in the vertical dimension under the bond pad, connected through via structures that extend downward to the substrate. This vertical arrangement provides ESD protection while preserving horizontal chip space.
2Reliability
If traditional ESD devices are used, then ESD protection is provided, but the devices fail due to thin underpass connections during ESD events
Solution Approach 1:
The connection path for ESD current is segmented into multiple robust via structures distributed under the bond pad. Instead of relying on a single thin underpass connection, the ESD current is divided and routed through multiple via structures that connect the ESD circuit to the substrate, thereby distributing the stress and reducing the risk of connection failure.
Solution Approach 2:
The via structures under the bond pad are designed with enhanced local quality - they are positioned strategically and sized appropriately to handle high ESD currents. These via structures have optimized dimensions and are placed in regions where they can effectively carry ESD current to the substrate without failing, providing localized reinforcement where it is most needed.
3Reliability
If larger ESD devices are used to improve protection capability, then ESD absorption capacity increases, but chip space consumption increases
Solution Approach 1:
The ESD circuit is extended in the vertical dimension rather than expanding horizontally. Multiple via structures connect the ESD circuit under the bond pad to the substrate at different depths and locations, providing enhanced ESD absorption capacity through vertical current paths that do not consume additional horizontal chip space.
Solution Approach 2:
The bond pad structure serves multiple functions: it provides the electrical connection for the external circuit and simultaneously houses the ESD protection circuit underneath it. This multi-functionality allows the ESD protection capability to be enhanced without dedicating separate chip space exclusively for ESD devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a low area, low resistance inductive shunt ESD network that effectively protects semiconductor devices from ESD events by using the through wafer via structure to connect the ESD network directly to the substrate, reducing the risk of damage and preserving valuable chip space.
Implementation Method 1
forming an ESD element having an inductive coil under the bond pad
Implementation Method 2
a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS
Data Source
AI summary
Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.